Lines Matching +full:lpddr4 +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[(dev)] = \
79 next->ptfv_list[(dev)] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[(dev)] += \
93 ((timing)->ptfv_list[(dev)] / \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
105 next->ptfv_list[w])) / \
106 (next->ptfv_list[w] + 1); \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
114 ((timing)->ptfv_list[(dev)])
119 u32 *curr = &timing->current_dram_clktree[idx]; in tegra210_emc_compare_update_delay()
120 u32 rate_mhz = timing->rate / 1000; in tegra210_emc_compare_update_delay()
123 tmdel = abs(*curr - measured); in tegra210_emc_compare_update_delay()
125 if (tmdel * 128 * rate_mhz / 1000000 > timing->tree_margin) { in tegra210_emc_compare_update_delay()
136 struct tegra210_emc_timing *curr = emc->last; in tegra210_emc_get_clktree_delay()
137 u32 rate_mhz = curr->rate / 1000; in tegra210_emc_get_clktree_delay()
142 clocks = tegra210_emc_actual_osc_clocks(curr->run_clocks); in tegra210_emc_get_clktree_delay()
148 for (d = 0; d < emc->num_devices; d++) { in tegra210_emc_get_clktree_delay()
150 msb = tegra210_emc_mrr_read(emc, 2 - d, 19); in tegra210_emc_get_clktree_delay()
151 lsb = tegra210_emc_mrr_read(emc, 2 - d, 18); in tegra210_emc_get_clktree_delay()
153 for (c = 0; c < emc->num_channels; c++) { in tegra210_emc_get_clktree_delay()
188 (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) in periodic_compensation_handler()
190 u32 i, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; in periodic_compensation_handler()
194 if (!next->periodic_training) in periodic_compensation_handler()
198 if (last->periodic_training && in periodic_compensation_handler()
199 (next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] & in periodic_compensation_handler()
258 struct tegra210_emc_timing *last = emc->last; in tegra210_emc_r21021_periodic_compensation()
261 if (last->periodic_training) { in tegra210_emc_r21021_periodic_compensation()
279 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_periodic_compensation()
284 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_periodic_compensation()
295 * 2. osc kick off - this assumes training and dvfs have set in tegra210_emc_r21021_periodic_compensation()
359 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; in tegra210_emc_r21021_set_clock()
364 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; in tegra210_emc_r21021_set_clock()
379 fake = tegra210_emc_find_timing(emc, last->rate * 1000UL); in tegra210_emc_r21021_set_clock()
385 if (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31)) in tegra210_emc_r21021_set_clock()
388 if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 && in tegra210_emc_r21021_set_clock()
389 last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) || in tegra210_emc_r21021_set_clock()
396 if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) && in tegra210_emc_r21021_set_clock()
403 src_clk_period = 1000000000 / last->rate; in tegra210_emc_r21021_set_clock()
404 dst_clk_period = 1000000000 / next->rate; in tegra210_emc_r21021_set_clock()
407 tZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4 - tFC_lpddr4; in tegra210_emc_r21021_set_clock()
417 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
420 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock()
430 emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices); in tegra210_emc_r21021_set_clock()
432 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
433 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate, in tegra210_emc_r21021_set_clock()
434 next->rate); in tegra210_emc_r21021_set_clock()
438 emc_dbg(emc, INFO, " num_channels: %u\n", emc->num_channels); in tegra210_emc_r21021_set_clock()
454 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
460 emc_auto_cal_config = next->emc_auto_cal_config; in tegra210_emc_r21021_set_clock()
476 if (next->periodic_training) { in tegra210_emc_r21021_set_clock()
479 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
484 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_r21021_set_clock()
499 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp & in tegra210_emc_r21021_set_clock()
504 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
506 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
508 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
510 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
513 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
516 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
521 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
527 emc_writel(emc, last->burst_regs in tegra210_emc_r21021_set_clock()
534 if ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
536 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
538 (((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
540 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] & in tegra210_emc_r21021_set_clock()
543 next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
545 last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_r21021_set_clock()
570 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & in tegra210_emc_r21021_set_clock()
587 emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2); in tegra210_emc_r21021_set_clock()
588 emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3); in tegra210_emc_r21021_set_clock()
589 emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4); in tegra210_emc_r21021_set_clock()
590 emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5); in tegra210_emc_r21021_set_clock()
591 emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6); in tegra210_emc_r21021_set_clock()
592 emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7); in tegra210_emc_r21021_set_clock()
593 emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8); in tegra210_emc_r21021_set_clock()
609 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
620 zq_wait_long = max(next->min_mrs_wait, in tegra210_emc_r21021_set_clock()
630 * Training code - removed. in tegra210_emc_r21021_set_clock()
639 emc_dbg(emc, SUB_STEPS, "Step 7.1: Bug 200024907 - Patch RP R2P"); in tegra210_emc_r21021_set_clock()
667 tRPST = (last->emc_mrw & 0x80) >> 7; in tegra210_emc_r21021_set_clock()
668 tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) + in tegra210_emc_r21021_set_clock()
673 next->burst_regs[EMC_RP_INDEX]); in tegra210_emc_r21021_set_clock()
675 if (last->burst_regs[EMC_RP_INDEX] < tRTM) { in tegra210_emc_r21021_set_clock()
676 if (tRTM > (last->burst_regs[EMC_R2P_INDEX] + in tegra210_emc_r21021_set_clock()
677 last->burst_regs[EMC_RP_INDEX])) { in tegra210_emc_r21021_set_clock()
678 R2P_war = tRTM - last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
679 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
680 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
684 last->burst_regs[EMC_RP_INDEX] - 63; in tegra210_emc_r21021_set_clock()
692 R2P_war = last->burst_regs[EMC_R2P_INDEX]; in tegra210_emc_r21021_set_clock()
693 RP_war = last->burst_regs[EMC_RP_INDEX]; in tegra210_emc_r21021_set_clock()
694 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX]; in tegra210_emc_r21021_set_clock()
698 W2P_war = last->burst_regs[EMC_W2P_INDEX] in tegra210_emc_r21021_set_clock()
699 + deltaTWATM - RP_war; in tegra210_emc_r21021_set_clock()
701 RP_war = RP_war + W2P_war - 63; in tegra210_emc_r21021_set_clock()
707 W2P_war = last->burst_regs[ in tegra210_emc_r21021_set_clock()
711 if ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) || in tegra210_emc_r21021_set_clock()
712 (last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) || in tegra210_emc_r21021_set_clock()
713 (last->burst_regs[EMC_RP_INDEX] ^ RP_war) || in tegra210_emc_r21021_set_clock()
714 (last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) { in tegra210_emc_r21021_set_clock()
728 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80; in tegra210_emc_r21021_set_clock()
729 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00; in tegra210_emc_r21021_set_clock()
731 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40; in tegra210_emc_r21021_set_clock()
732 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0; in tegra210_emc_r21021_set_clock()
737 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
738 emc_writel(emc, next->emc_mrw2, EMC_MRW2); in tegra210_emc_r21021_set_clock()
748 for (i = 0; i < next->num_burst; i++) { in tegra210_emc_r21021_set_clock()
749 const u16 *offsets = emc->offsets->burst; in tegra210_emc_r21021_set_clock()
755 value = next->burst_regs[i]; in tegra210_emc_r21021_set_clock()
820 (next->run_clocks & EMC_MRW_MRW_OP_MASK); in tegra210_emc_r21021_set_clock()
824 /* Per channel burst registers. */ in tegra210_emc_r21021_set_clock()
827 for (i = 0; i < next->num_burst_per_ch; i++) { in tegra210_emc_r21021_set_clock()
829 emc->offsets->burst_per_channel; in tegra210_emc_r21021_set_clock()
847 /* Filter out second channel if not in DUAL_CHANNEL mode. */ in tegra210_emc_r21021_set_clock()
848 if (emc->num_channels < 2 && burst[i].bank >= 1) in tegra210_emc_r21021_set_clock()
852 next->burst_reg_per_ch[i], burst[i].offset); in tegra210_emc_r21021_set_clock()
854 next->burst_reg_per_ch[i], in tegra210_emc_r21021_set_clock()
861 for (i = 0; i < next->vref_num; i++) { in tegra210_emc_r21021_set_clock()
863 emc->offsets->vref_per_channel; in tegra210_emc_r21021_set_clock()
868 if (emc->num_channels < 2 && vref[i].bank >= 1) in tegra210_emc_r21021_set_clock()
872 next->vref_perch_regs[i], vref[i].offset); in tegra210_emc_r21021_set_clock()
873 emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i], in tegra210_emc_r21021_set_clock()
880 for (i = 0; i < next->num_trim; i++) { in tegra210_emc_r21021_set_clock()
881 const u16 *offsets = emc->offsets->trim; in tegra210_emc_r21021_set_clock()
905 next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
906 emc_writel(emc, next->trim_regs[i], offsets[i]); in tegra210_emc_r21021_set_clock()
910 /* Per channel trimmers. */ in tegra210_emc_r21021_set_clock()
913 for (i = 0; i < next->num_trim_per_ch; i++) { in tegra210_emc_r21021_set_clock()
915 &emc->offsets->trim_per_channel[0]; in tegra210_emc_r21021_set_clock()
921 if (emc->num_channels < 2 && trim[i].bank >= 1) in tegra210_emc_r21021_set_clock()
945 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
947 next->trim_perch_regs[i], offset); in tegra210_emc_r21021_set_clock()
953 for (i = 0; i < next->num_mc_regs; i++) { in tegra210_emc_r21021_set_clock()
954 const u16 *offsets = emc->offsets->burst_mc; in tegra210_emc_r21021_set_clock()
955 u32 *values = next->burst_mc_regs; in tegra210_emc_r21021_set_clock()
959 mc_writel(emc->mc, values[i], offsets[i]); in tegra210_emc_r21021_set_clock()
963 if (next->rate < last->rate) { in tegra210_emc_r21021_set_clock()
964 const u16 *la = emc->offsets->la_scale; in tegra210_emc_r21021_set_clock()
968 for (i = 0; i < next->num_up_down; i++) { in tegra210_emc_r21021_set_clock()
970 next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
971 mc_writel(emc->mc, next->la_scale_regs[i], la[i]); in tegra210_emc_r21021_set_clock()
976 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_r21021_set_clock()
980 * LPDDR4 section A. in tegra210_emc_r21021_set_clock()
984 value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX]; in tegra210_emc_r21021_set_clock()
1001 * LPDDR4 and DDR3 common section. in tegra210_emc_r21021_set_clock()
1014 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1016 (last->burst_regs[EMC_MRW6_INDEX] & in tegra210_emc_r21021_set_clock()
1018 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1020 (last->burst_regs[EMC_MRW14_INDEX] & in tegra210_emc_r21021_set_clock()
1023 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1025 (next->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1027 (last->burst_regs[EMC_MRW7_INDEX] & in tegra210_emc_r21021_set_clock()
1030 (next->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1032 (last->burst_regs[EMC_MRW15_INDEX] & in tegra210_emc_r21021_set_clock()
1037 if (emc->num_devices < 2) in tegra210_emc_r21021_set_clock()
1056 value = (1000 * fake->dram_timings[T_RP]) / src_clk_period; in tegra210_emc_r21021_set_clock()
1065 delay += (1000 * fake->dram_timings[T_RP]) / in tegra210_emc_r21021_set_clock()
1067 delay += 4000 * fake->dram_timings[T_RFC]; in tegra210_emc_r21021_set_clock()
1089 delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) + in tegra210_emc_r21021_set_clock()
1090 (1000 * fake->dram_timings[T_RFC] / src_clk_period)); in tegra210_emc_r21021_set_clock()
1112 * And finally - trigger the clock change. in tegra210_emc_r21021_set_clock()
1138 if (emc->num_devices <= 1) in tegra210_emc_r21021_set_clock()
1155 zq_latch_dvfs_wait_time = (s32)tZQCAL_lpddr4_fc_adj - t; in tegra210_emc_r21021_set_clock()
1157 zq_latch_dvfs_wait_time = tZQCAL_lpddr4_fc_adj - in tegra210_emc_r21021_set_clock()
1158 div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1165 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n", in tegra210_emc_r21021_set_clock()
1166 next->dram_timings[T_PDEX]); in tegra210_emc_r21021_set_clock()
1171 delay = div_o3(1000 * next->dram_timings[T_PDEX], in tegra210_emc_r21021_set_clock()
1174 if (emc->num_devices < 2) { in tegra210_emc_r21021_set_clock()
1232 * LPDDR4 Conditional Training Kickoff. Removed. in tegra210_emc_r21021_set_clock()
1251 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0); in tegra210_emc_r21021_set_clock()
1252 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1254 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0); in tegra210_emc_r21021_set_clock()
1257 ccfifo_writel(emc, next->emc_emrs & in tegra210_emc_r21021_set_clock()
1259 ccfifo_writel(emc, next->emc_emrs2 & in tegra210_emc_r21021_set_clock()
1261 ccfifo_writel(emc, next->emc_mrs | in tegra210_emc_r21021_set_clock()
1288 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1303 if (emc->num_devices > 1) { in tegra210_emc_r21021_set_clock()
1315 delay = (1250000 - ramp_up_wait) / dst_clk_period; in tegra210_emc_r21021_set_clock()
1320 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX], in tegra210_emc_r21021_set_clock()
1349 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1353 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] & in tegra210_emc_r21021_set_clock()
1370 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1375 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] & in tegra210_emc_r21021_set_clock()
1407 if (next->rate > last->rate) { in tegra210_emc_r21021_set_clock()
1408 for (i = 0; i < next->num_up_down; i++) in tegra210_emc_r21021_set_clock()
1409 mc_writel(emc->mc, next->la_scale_regs[i], in tegra210_emc_r21021_set_clock()
1410 emc->offsets->la_scale[i]); in tegra210_emc_r21021_set_clock()
1423 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1425 emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX], in tegra210_emc_r21021_set_clock()
1436 emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1439 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX], in tegra210_emc_r21021_set_clock()
1451 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG); in tegra210_emc_r21021_set_clock()
1453 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp, in tegra210_emc_r21021_set_clock()
1455 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL); in tegra210_emc_r21021_set_clock()
1465 next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX], in tegra210_emc_r21021_set_clock()
1492 * Re-enable autocal. in tegra210_emc_r21021_set_clock()
1494 emc_dbg(emc, STEPS, "Step 30: Re-enable DLL and AUTOCAL\n"); in tegra210_emc_r21021_set_clock()
1496 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) { in tegra210_emc_r21021_set_clock()
1508 emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG); in tegra210_emc_r21021_set_clock()