Lines Matching full:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) in rts5249_get_ic_version() argument
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5249_get_ic_version()
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5249_fill_driving() argument
42 drive_sel = pcr->sd30_drive_sel_3v3; in rts5249_fill_driving()
45 drive_sel = pcr->sd30_drive_sel_1v8; in rts5249_fill_driving()
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, in rts5249_fill_driving()
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, in rts5249_fill_driving()
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, in rts5249_fill_driving()
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx_base_fetch_vendor_settings() argument
58 struct pci_dev *pdev = pcr->pci; in rtsx_base_fetch_vendor_settings()
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx_base_fetch_vendor_settings()
65 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx_base_fetch_vendor_settings()
69 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx_base_fetch_vendor_settings()
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx_base_fetch_vendor_settings()
71 pcr->card_drive_sel &= 0x3F; in rtsx_base_fetch_vendor_settings()
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); in rtsx_base_fetch_vendor_settings()
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx_base_fetch_vendor_settings()
77 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rtsx_base_fetch_vendor_settings()
78 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg); in rtsx_base_fetch_vendor_settings()
81 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx_base_fetch_vendor_settings()
82 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx_base_fetch_vendor_settings()
84 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx_base_fetch_vendor_settings()
87 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) in rts5249_init_from_cfg() argument
89 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_cfg()
91 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_init_from_cfg()
92 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5249_init_from_cfg()
94 rtsx_pci_disable_oobs_polling(pcr); in rts5249_init_from_cfg()
96 rtsx_pci_enable_oobs_polling(pcr); in rts5249_init_from_cfg()
101 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5249_init_from_cfg()
105 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) in rts52xa_force_power_down() argument
108 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rts52xa_force_power_down()
109 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rts52xa_force_power_down()
110 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rts52xa_force_power_down()
113 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts52xa_force_power_down()
117 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, in rts52xa_force_power_down()
119 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts52xa_force_power_down()
120 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts52xa_force_power_down()
123 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN); in rts52xa_force_power_down()
126 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) in rts52xa_save_content_from_efuse() argument
134 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
138 pcr_dbg(pcr, "Enable efuse por!"); in rts52xa_save_content_from_efuse()
139 pcr_dbg(pcr, "save efuse to autoload"); in rts52xa_save_content_from_efuse()
141 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); in rts52xa_save_content_from_efuse()
142 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
146 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
150 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
156 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
158 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
162 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
166 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
167 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
170 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_from_efuse()
171 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
172 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_from_efuse()
173 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
178 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
181 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
183 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
187 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
191 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
192 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
194 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); in rts52xa_save_content_from_efuse()
195 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
197 pcr_dbg(pcr, "Disable efuse por!"); in rts52xa_save_content_from_efuse()
200 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) in rts52xa_save_content_to_autoload_space() argument
204 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); in rts52xa_save_content_to_autoload_space()
206 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); in rts52xa_save_content_to_autoload_space()
208 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, in rts52xa_save_content_to_autoload_space()
211 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_to_autoload_space()
214 pcr_dbg(pcr, "Power ON efuse!"); in rts52xa_save_content_to_autoload_space()
216 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
218 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); in rts52xa_save_content_to_autoload_space()
220 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
223 pcr_dbg(pcr, "Load from autoload"); in rts52xa_save_content_to_autoload_space()
224 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); in rts52xa_save_content_to_autoload_space()
225 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_to_autoload_space()
226 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
227 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_to_autoload_space()
228 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
232 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) in rts5249_extra_init_hw() argument
234 struct rtsx_cr_option *option = &(pcr->option); in rts5249_extra_init_hw()
236 rts5249_init_from_cfg(pcr); in rts5249_extra_init_hw()
238 rtsx_pci_init_cmd(pcr); in rts5249_extra_init_hw()
240 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
241 rts52xa_save_content_to_autoload_space(pcr); in rts5249_extra_init_hw()
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); in rts5249_extra_init_hw()
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); in rts5249_extra_init_hw()
248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); in rts5249_extra_init_hw()
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); in rts5249_extra_init_hw()
251 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); in rts5249_extra_init_hw()
253 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); in rts5249_extra_init_hw()
255 rts5249_fill_driving(pcr, OUTPUT_3V3); in rts5249_extra_init_hw()
256 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5249_extra_init_hw()
257 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); in rts5249_extra_init_hw()
259 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); in rts5249_extra_init_hw()
261 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); in rts5249_extra_init_hw()
263 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
264 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); in rts5249_extra_init_hw()
265 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, in rts5249_extra_init_hw()
269 if (pcr->rtd3_en) { in rts5249_extra_init_hw()
270 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
271 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
272 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30); in rts5249_extra_init_hw()
274 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
275 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33); in rts5249_extra_init_hw()
278 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
279 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
280 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts5249_extra_init_hw()
282 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); in rts5249_extra_init_hw()
283 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
293 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
296 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
299 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); in rts5249_extra_init_hw()
300 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
301 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts5249_extra_init_hw()
303 pcr_dbg(pcr, "Power OFF efuse!"); in rts5249_extra_init_hw()
309 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) in rts5249_optimize_phy() argument
313 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); in rts5249_optimize_phy()
317 err = rtsx_pci_write_phy_register(pcr, PHY_REV, in rts5249_optimize_phy()
328 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, in rts5249_optimize_phy()
334 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts5249_optimize_phy()
341 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, in rts5249_optimize_phy()
348 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, in rts5249_optimize_phy()
355 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, in rts5249_optimize_phy()
359 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, in rts5249_optimize_phy()
363 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, in rts5249_optimize_phy()
369 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, in rts5249_optimize_phy()
375 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) in rtsx_base_turn_on_led() argument
377 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); in rtsx_base_turn_on_led()
380 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) in rtsx_base_turn_off_led() argument
382 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); in rtsx_base_turn_off_led()
385 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_enable_auto_blink() argument
387 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); in rtsx_base_enable_auto_blink()
390 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_disable_auto_blink() argument
392 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); in rtsx_base_disable_auto_blink()
395 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_on() argument
398 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_on()
401 rtsx_pci_enable_ocp(pcr); in rtsx_base_card_power_on()
403 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
408 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
414 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
415 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
419 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
422 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_off() argument
424 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_off()
427 rtsx_pci_disable_ocp(pcr); in rtsx_base_card_power_off()
429 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); in rtsx_base_card_power_off()
431 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); in rtsx_base_card_power_off()
435 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_base_switch_output_voltage() argument
442 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
449 if (CHK_PCI_PID(pcr, 0x5249)) { in rtsx_base_switch_output_voltage()
450 err = rtsx_pci_update_phy(pcr, PHY_BACR, in rtsx_base_switch_output_voltage()
457 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
463 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); in rtsx_base_switch_output_voltage()
468 rtsx_pci_init_cmd(pcr); in rtsx_base_switch_output_voltage()
469 rts5249_fill_driving(pcr, voltage); in rtsx_base_switch_output_voltage()
470 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_switch_output_voltage()
538 void rts5249_init_params(struct rtsx_pcr *pcr) in rts5249_init_params() argument
540 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_params()
542 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5249_init_params()
543 pcr->num_slots = 2; in rts5249_init_params()
544 pcr->ops = &rts5249_pcr_ops; in rts5249_init_params()
546 pcr->flags = 0; in rts5249_init_params()
547 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5249_init_params()
548 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
549 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
550 pcr->aspm_en = ASPM_L1_EN; in rts5249_init_params()
551 pcr->aspm_mode = ASPM_MODE_CFG; in rts5249_init_params()
552 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); in rts5249_init_params()
553 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5249_init_params()
555 pcr->ic_version = rts5249_get_ic_version(pcr); in rts5249_init_params()
556 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; in rts5249_init_params()
557 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; in rts5249_init_params()
558 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; in rts5249_init_params()
559 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; in rts5249_init_params()
561 pcr->reg_pm_ctrl3 = PM_CTRL3; in rts5249_init_params()
577 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) in rts524a_write_phy() argument
581 return __rtsx_pci_write_phy_register(pcr, addr, val); in rts524a_write_phy()
584 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rts524a_read_phy() argument
588 return __rtsx_pci_read_phy_register(pcr, addr, val); in rts524a_read_phy()
591 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) in rts524a_optimize_phy() argument
595 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts524a_optimize_phy()
600 rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts524a_optimize_phy()
603 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
606 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_optimize_phy()
607 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
609 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, in rts524a_optimize_phy()
612 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, in rts524a_optimize_phy()
615 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, in rts524a_optimize_phy()
617 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, in rts524a_optimize_phy()
627 rtsx_pci_write_phy_register(pcr, PHY_ANA08, in rts524a_optimize_phy()
634 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) in rts524a_extra_init_hw() argument
636 rts5249_extra_init_hw(pcr); in rts524a_extra_init_hw()
638 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts524a_extra_init_hw()
640 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts524a_extra_init_hw()
641 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, in rts524a_extra_init_hw()
643 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts524a_extra_init_hw()
644 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_extra_init_hw()
645 rtsx_pci_write_register(pcr, LDO_DV18_CFG, in rts524a_extra_init_hw()
647 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts524a_extra_init_hw()
649 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
651 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
653 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts524a_extra_init_hw()
655 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, in rts524a_extra_init_hw()
662 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5250_set_l1off_cfg_sub_d0() argument
664 struct rtsx_cr_option *option = &(pcr->option); in rts5250_set_l1off_cfg_sub_d0()
666 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5250_set_l1off_cfg_sub_d0()
671 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5250_set_l1off_cfg_sub_d0()
672 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5250_set_l1off_cfg_sub_d0()
685 if (rtsx_check_dev_flag(pcr, in rts5250_set_l1off_cfg_sub_d0()
693 rtsx_set_l1off_sub(pcr, val); in rts5250_set_l1off_cfg_sub_d0()
713 void rts524a_init_params(struct rtsx_pcr *pcr) in rts524a_init_params() argument
715 rts5249_init_params(pcr); in rts524a_init_params()
716 pcr->aspm_mode = ASPM_MODE_REG; in rts524a_init_params()
717 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); in rts524a_init_params()
718 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts524a_init_params()
719 pcr->option.ltr_l1off_snooze_sspwrgate = in rts524a_init_params()
722 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts524a_init_params()
723 pcr->ops = &rts524a_pcr_ops; in rts524a_init_params()
725 pcr->option.ocp_en = 1; in rts524a_init_params()
726 if (pcr->option.ocp_en) in rts524a_init_params()
727 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts524a_init_params()
728 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts524a_init_params()
729 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; in rts524a_init_params()
733 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) in rts525a_card_power_on() argument
735 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts525a_card_power_on()
737 return rtsx_base_card_power_on(pcr, card); in rts525a_card_power_on()
740 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts525a_switch_output_voltage() argument
744 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
746 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); in rts525a_switch_output_voltage()
749 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
751 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, in rts525a_switch_output_voltage()
758 rtsx_pci_init_cmd(pcr); in rts525a_switch_output_voltage()
759 rts5249_fill_driving(pcr, voltage); in rts525a_switch_output_voltage()
760 return rtsx_pci_send_cmd(pcr, 100); in rts525a_switch_output_voltage()
763 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) in rts525a_optimize_phy() argument
767 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts525a_optimize_phy()
772 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, in rts525a_optimize_phy()
777 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, in rts525a_optimize_phy()
781 if (is_version(pcr, 0x525A, IC_VER_A)) in rts525a_optimize_phy()
782 rtsx_pci_write_phy_register(pcr, _PHY_REV0, in rts525a_optimize_phy()
789 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) in rts525a_extra_init_hw() argument
791 rts5249_extra_init_hw(pcr); in rts525a_extra_init_hw()
793 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); in rts525a_extra_init_hw()
795 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts525a_extra_init_hw()
796 if (is_version(pcr, 0x525A, IC_VER_A)) { in rts525a_extra_init_hw()
797 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, in rts525a_extra_init_hw()
799 rtsx_pci_write_register(pcr, RREF_CFG, in rts525a_extra_init_hw()
801 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts525a_extra_init_hw()
803 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts525a_extra_init_hw()
805 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, in rts525a_extra_init_hw()
807 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, in rts525a_extra_init_hw()
809 rtsx_pci_write_register(pcr, OOBS_CONFIG, in rts525a_extra_init_hw()
831 void rts525a_init_params(struct rtsx_pcr *pcr) in rts525a_init_params() argument
833 rts5249_init_params(pcr); in rts525a_init_params()
834 pcr->aspm_mode = ASPM_MODE_REG; in rts525a_init_params()
835 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); in rts525a_init_params()
836 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts525a_init_params()
837 pcr->option.ltr_l1off_snooze_sspwrgate = in rts525a_init_params()
840 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts525a_init_params()
841 pcr->ops = &rts525a_pcr_ops; in rts525a_init_params()
843 pcr->option.ocp_en = 1; in rts525a_init_params()
844 if (pcr->option.ocp_en) in rts525a_init_params()
845 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts525a_init_params()
846 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts525a_init_params()
847 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; in rts525a_init_params()