Lines Matching full:pcr
17 static u8 rts5264_get_ic_version(struct rtsx_pcr *pcr) in rts5264_get_ic_version() argument
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5264_get_ic_version()
25 static void rts5264_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5264_fill_driving() argument
43 drive_sel = pcr->sd30_drive_sel_3v3; in rts5264_fill_driving()
46 drive_sel = pcr->sd30_drive_sel_1v8; in rts5264_fill_driving()
49 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, in rts5264_fill_driving()
51 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, in rts5264_fill_driving()
53 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, in rts5264_fill_driving()
57 static void rts5264_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) in rts5264_force_power_down() argument
60 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rts5264_force_power_down()
61 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rts5264_force_power_down()
62 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rts5264_force_power_down()
66 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5264_force_power_down()
70 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1, in rts5264_force_power_down()
72 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5264_force_power_down()
73 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_force_power_down()
76 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_force_power_down()
78 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); in rts5264_force_power_down()
79 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5264_force_power_down()
81 rtsx_pci_write_register(pcr, RTS5264_FW_CTL, in rts5264_force_power_down()
83 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, in rts5264_force_power_down()
87 rtsx_pci_write_register(pcr, RTS5264_REG_FPDCTL, in rts5264_force_power_down()
91 static int rts5264_enable_auto_blink(struct rtsx_pcr *pcr) in rts5264_enable_auto_blink() argument
93 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5264_enable_auto_blink()
97 static int rts5264_disable_auto_blink(struct rtsx_pcr *pcr) in rts5264_disable_auto_blink() argument
99 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5264_disable_auto_blink()
103 static int rts5264_turn_on_led(struct rtsx_pcr *pcr) in rts5264_turn_on_led() argument
105 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5264_turn_on_led()
109 static int rts5264_turn_off_led(struct rtsx_pcr *pcr) in rts5264_turn_off_led() argument
111 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5264_turn_off_led()
141 static int rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) in rts5264_sd_set_sample_push_timing_sd30() argument
143 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK in rts5264_sd_set_sample_push_timing_sd30()
145 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5264_sd_set_sample_push_timing_sd30()
146 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, in rts5264_sd_set_sample_push_timing_sd30()
148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5264_sd_set_sample_push_timing_sd30()
153 static int rts5264_card_power_on(struct rtsx_pcr *pcr, int card) in rts5264_card_power_on() argument
155 struct rtsx_cr_option *option = &pcr->option; in rts5264_card_power_on()
158 rtsx_pci_enable_ocp(pcr); in rts5264_card_power_on()
160 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5264_card_power_on()
163 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG1, in rts5264_card_power_on()
165 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, in rts5264_card_power_on()
167 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, in rts5264_card_power_on()
172 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); in rts5264_card_power_on()
175 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, in rts5264_card_power_on()
177 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, in rts5264_card_power_on()
179 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); in rts5264_card_power_on()
180 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, in rts5264_card_power_on()
184 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); in rts5264_card_power_on()
185 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, in rts5264_card_power_on()
189 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || in rts5264_card_power_on()
190 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) in rts5264_card_power_on()
191 rts5264_sd_set_sample_push_timing_sd30(pcr); in rts5264_card_power_on()
196 static int rts5264_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts5264_switch_output_voltage() argument
198 rtsx_pci_write_register(pcr, RTS5264_CARD_PWR_CTL, in rts5264_switch_output_voltage()
203 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, in rts5264_switch_output_voltage()
205 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG, in rts5264_switch_output_voltage()
207 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5264_switch_output_voltage()
211 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, in rts5264_switch_output_voltage()
213 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG, in rts5264_switch_output_voltage()
215 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5264_switch_output_voltage()
223 rts5264_fill_driving(pcr, voltage); in rts5264_switch_output_voltage()
228 static void rts5264_stop_cmd(struct rtsx_pcr *pcr) in rts5264_stop_cmd() argument
230 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); in rts5264_stop_cmd()
231 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); in rts5264_stop_cmd()
232 rtsx_pci_write_register(pcr, DMACTL, DMA_RST, DMA_RST); in rts5264_stop_cmd()
233 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); in rts5264_stop_cmd()
236 static void rts5264_card_before_power_off(struct rtsx_pcr *pcr) in rts5264_card_before_power_off() argument
238 rts5264_stop_cmd(pcr); in rts5264_card_before_power_off()
239 rts5264_switch_output_voltage(pcr, OUTPUT_3V3); in rts5264_card_before_power_off()
242 static int rts5264_card_power_off(struct rtsx_pcr *pcr, int card) in rts5264_card_power_off() argument
246 rts5264_card_before_power_off(pcr); in rts5264_card_power_off()
247 err = rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL, in rts5264_card_power_off()
250 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5264_card_power_off()
252 if (pcr->option.ocp_en) in rts5264_card_power_off()
253 rtsx_pci_disable_ocp(pcr); in rts5264_card_power_off()
258 static void rts5264_enable_ocp(struct rtsx_pcr *pcr) in rts5264_enable_ocp() argument
263 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, in rts5264_enable_ocp()
266 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, in rts5264_enable_ocp()
269 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, in rts5264_enable_ocp()
272 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, in rts5264_enable_ocp()
278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); in rts5264_enable_ocp()
282 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, val); in rts5264_enable_ocp()
286 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, val); in rts5264_enable_ocp()
289 static void rts5264_disable_ocp(struct rtsx_pcr *pcr) in rts5264_disable_ocp() argument
295 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5264_disable_ocp()
298 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, 0); in rts5264_disable_ocp()
301 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, 0); in rts5264_disable_ocp()
303 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, in rts5264_disable_ocp()
305 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, in rts5264_disable_ocp()
307 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, in rts5264_disable_ocp()
309 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, RTS5264_POW_VDET, 0); in rts5264_disable_ocp()
312 static void rts5264_init_ocp(struct rtsx_pcr *pcr) in rts5264_init_ocp() argument
314 struct rtsx_cr_option *option = &pcr->option; in rts5264_init_ocp()
319 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, in rts5264_init_ocp()
321 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, in rts5264_init_ocp()
325 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, in rts5264_init_ocp()
327 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, in rts5264_init_ocp()
331 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, in rts5264_init_ocp()
333 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, in rts5264_init_ocp()
337 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, in rts5264_init_ocp()
341 val = pcr->hw_param.ocp_glitch; in rts5264_init_ocp()
342 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); in rts5264_init_ocp()
345 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0, in rts5264_init_ocp()
347 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0, in rts5264_init_ocp()
349 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0, in rts5264_init_ocp()
351 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, in rts5264_init_ocp()
356 static int rts5264_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val) in rts5264_get_ocpstat2() argument
358 return rtsx_pci_read_register(pcr, RTS5264_OCP_VDD3_STS, val); in rts5264_get_ocpstat2()
361 static int rts5264_get_ovpstat(struct rtsx_pcr *pcr, u8 *val) in rts5264_get_ovpstat() argument
363 return rtsx_pci_read_register(pcr, RTS5264_OVP_STS, val); in rts5264_get_ovpstat()
366 static void rts5264_clear_ocpstat(struct rtsx_pcr *pcr) in rts5264_clear_ocpstat() argument
374 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); in rts5264_clear_ocpstat()
375 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, in rts5264_clear_ocpstat()
378 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, in rts5264_clear_ocpstat()
384 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5264_clear_ocpstat()
385 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, in rts5264_clear_ocpstat()
387 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, in rts5264_clear_ocpstat()
391 static void rts5264_process_ocp(struct rtsx_pcr *pcr) in rts5264_process_ocp() argument
393 if (!pcr->option.ocp_en) in rts5264_process_ocp()
396 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); in rts5264_process_ocp()
397 rts5264_get_ocpstat2(pcr, &pcr->ocp_stat2); in rts5264_process_ocp()
398 rts5264_get_ovpstat(pcr, &pcr->ovp_stat); in rts5264_process_ocp()
400 if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) || in rts5264_process_ocp()
401 (pcr->ocp_stat2 & (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) || in rts5264_process_ocp()
402 (pcr->ovp_stat & (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) { in rts5264_process_ocp()
403 rts5264_clear_ocpstat(pcr); in rts5264_process_ocp()
404 rts5264_card_power_off(pcr, RTSX_SD_CARD); in rts5264_process_ocp()
405 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rts5264_process_ocp()
406 pcr->ocp_stat = 0; in rts5264_process_ocp()
407 pcr->ocp_stat2 = 0; in rts5264_process_ocp()
408 pcr->ovp_stat = 0; in rts5264_process_ocp()
412 static void rts5264_init_from_hw(struct rtsx_pcr *pcr) in rts5264_init_from_hw() argument
414 struct pci_dev *pdev = pcr->pci; in rts5264_init_from_hw()
419 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_init_from_hw()
423 rtsx_pci_write_register(pcr, RTS5264_EFUSE_ADDR, in rts5264_init_from_hw()
425 rtsx_pci_write_register(pcr, RTS5264_EFUSE_CTL, in rts5264_init_from_hw()
431 rtsx_pci_read_register(pcr, RTS5264_EFUSE_CTL, &tmp); in rts5264_init_from_hw()
435 rtsx_pci_read_register(pcr, RTS5264_EFUSE_READ_DATA, &tmp); in rts5264_init_from_hw()
437 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid); in rts5264_init_from_hw()
440 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2); in rts5264_init_from_hw()
444 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_init_from_hw()
446 pcr_dbg(pcr, "Disable efuse por!\n"); in rts5264_init_from_hw()
467 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2); in rts5264_init_from_hw()
470 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rts5264_init_from_hw()
474 pcr->rtd3_en = rts5264_reg_to_rtd3(lval2); in rts5264_init_from_hw()
477 pcr->flags |= PCR_REVERSE_SOCKET; in rts5264_init_from_hw()
480 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1); in rts5264_init_from_hw()
482 pcr->aspm_en = rts5264_reg_to_aspm(lval1); in rts5264_init_from_hw()
483 pcr->sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1); in rts5264_init_from_hw()
484 pcr->sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1); in rts5264_init_from_hw()
488 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF)); in rts5264_init_from_hw()
489 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF)); in rts5264_init_from_hw()
490 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF)); in rts5264_init_from_hw()
491 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF)); in rts5264_init_from_hw()
492 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF)); in rts5264_init_from_hw()
493 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF)); in rts5264_init_from_hw()
494 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF)); in rts5264_init_from_hw()
502 static void rts5264_init_from_cfg(struct rtsx_pcr *pcr) in rts5264_init_from_cfg() argument
504 struct rtsx_cr_option *option = &pcr->option; in rts5264_init_from_cfg()
506 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5264_init_from_cfg()
508 rtsx_pci_disable_oobs_polling(pcr); in rts5264_init_from_cfg()
510 rtsx_pci_enable_oobs_polling(pcr); in rts5264_init_from_cfg()
512 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); in rts5264_init_from_cfg()
516 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5264_init_from_cfg()
520 static int rts5264_extra_init_hw(struct rtsx_pcr *pcr) in rts5264_extra_init_hw() argument
522 struct rtsx_cr_option *option = &pcr->option; in rts5264_extra_init_hw()
524 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1, in rts5264_extra_init_hw()
526 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); in rts5264_extra_init_hw()
528 rts5264_init_from_cfg(pcr); in rts5264_extra_init_hw()
529 rts5264_init_from_hw(pcr); in rts5264_extra_init_hw()
532 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_extra_init_hw()
534 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2, in rts5264_extra_init_hw()
536 rtsx_pci_write_register(pcr, RTS5264_REG_LDO12_CFG, in rts5264_extra_init_hw()
538 rtsx_pci_write_register(pcr, CDGW, 0xFF, 0x01); in rts5264_extra_init_hw()
539 rtsx_pci_write_register(pcr, RTS5264_CKMUX_MBIAS_PWR, in rts5264_extra_init_hw()
541 rtsx_pci_write_register(pcr, RTS5264_CMD_OE_START_EARLY, in rts5264_extra_init_hw()
544 rtsx_pci_write_register(pcr, RTS5264_DAT_OE_START_EARLY, in rts5264_extra_init_hw()
547 rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D); in rts5264_extra_init_hw()
549 rtsx_pci_write_register(pcr, RTS5264_PWR_CUT, in rts5264_extra_init_hw()
551 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, in rts5264_extra_init_hw()
553 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); in rts5264_extra_init_hw()
554 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, in rts5264_extra_init_hw()
558 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, in rts5264_extra_init_hw()
560 rtsx_pci_write_register(pcr, PCLK_CTL, in rts5264_extra_init_hw()
564 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); in rts5264_extra_init_hw()
567 rts5264_fill_driving(pcr, OUTPUT_3V3); in rts5264_extra_init_hw()
569 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5264_extra_init_hw()
570 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); in rts5264_extra_init_hw()
572 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); in rts5264_extra_init_hw()
579 rtsx_pci_write_register(pcr, PETXCFG, in rts5264_extra_init_hw()
582 rtsx_pci_write_register(pcr, PETXCFG, in rts5264_extra_init_hw()
585 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFF); in rts5264_extra_init_hw()
586 rtsx_pci_write_register(pcr, RBCTL, U_AUTO_DMA_EN_MASK, 0); in rts5264_extra_init_hw()
587 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4, in rts5264_extra_init_hw()
590 if (pcr->rtd3_en) { in rts5264_extra_init_hw()
591 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5264_extra_init_hw()
592 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_extra_init_hw()
595 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5264_extra_init_hw()
596 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL, in rts5264_extra_init_hw()
599 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00); in rts5264_extra_init_hw()
602 rtsx_pci_write_register(pcr, RTS5264_FW_CTL, in rts5264_extra_init_hw()
608 static void rts5264_enable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5264_enable_aspm() argument
613 if (pcr->aspm_enabled == enable) in rts5264_enable_aspm()
616 val |= (pcr->aspm_en & 0x02); in rts5264_enable_aspm()
617 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5264_enable_aspm()
618 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5264_enable_aspm()
619 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); in rts5264_enable_aspm()
620 pcr->aspm_enabled = enable; in rts5264_enable_aspm()
623 static void rts5264_disable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5264_disable_aspm() argument
628 if (pcr->aspm_enabled == enable) in rts5264_disable_aspm()
631 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5264_disable_aspm()
633 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5264_disable_aspm()
634 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in rts5264_disable_aspm()
636 pcr->aspm_enabled = enable; in rts5264_disable_aspm()
639 static void rts5264_set_aspm(struct rtsx_pcr *pcr, bool enable) in rts5264_set_aspm() argument
642 rts5264_enable_aspm(pcr, true); in rts5264_set_aspm()
644 rts5264_disable_aspm(pcr, false); in rts5264_set_aspm()
647 static void rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5264_set_l1off_cfg_sub_d0() argument
649 struct rtsx_cr_option *option = &(pcr->option); in rts5264_set_l1off_cfg_sub_d0()
651 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5264_set_l1off_cfg_sub_d0()
656 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5264_set_l1off_cfg_sub_d0()
657 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5264_set_l1off_cfg_sub_d0()
670 if (rtsx_check_dev_flag(pcr, in rts5264_set_l1off_cfg_sub_d0()
678 rtsx_set_l1off_sub(pcr, val); in rts5264_set_l1off_cfg_sub_d0()
706 int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, in rts5264_pci_switch_clock() argument
726 err = rtsx_pci_write_register(pcr, SD_CFG1, in rts5264_pci_switch_clock()
732 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); in rts5264_pci_switch_clock()
737 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", in rts5264_pci_switch_clock()
738 clk, pcr->cur_clock); in rts5264_pci_switch_clock()
740 if (clk == pcr->cur_clock) in rts5264_pci_switch_clock()
743 if (pcr->ops->conv_clk_and_div_n) in rts5264_pci_switch_clock()
744 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); in rts5264_pci_switch_clock()
756 if (pcr->ops->conv_clk_and_div_n) { in rts5264_pci_switch_clock()
757 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, in rts5264_pci_switch_clock()
759 n = pcr->ops->conv_clk_and_div_n(dbl_clk, in rts5264_pci_switch_clock()
768 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); in rts5264_pci_switch_clock()
794 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); in rts5264_pci_switch_clock()
796 rtsx_pci_init_cmd(pcr); in rts5264_pci_switch_clock()
797 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rts5264_pci_switch_clock()
799 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5264_pci_switch_clock()
801 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rts5264_pci_switch_clock()
802 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, in rts5264_pci_switch_clock()
804 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rts5264_pci_switch_clock()
806 if (is_version(pcr, 0x5264, IC_VER_A)) { in rts5264_pci_switch_clock()
807 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rts5264_pci_switch_clock()
808 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_CARD_CLK_SRC2, in rts5264_pci_switch_clock()
811 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in rts5264_pci_switch_clock()
812 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_SYS_DUMMY_1, in rts5264_pci_switch_clock()
817 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5264_pci_switch_clock()
819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5264_pci_switch_clock()
821 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5264_pci_switch_clock()
823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5264_pci_switch_clock()
827 err = rtsx_pci_send_cmd(pcr, 2000); in rts5264_pci_switch_clock()
833 err = rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); in rts5264_pci_switch_clock()
837 pcr->cur_clock = clk; in rts5264_pci_switch_clock()
841 void rts5264_init_params(struct rtsx_pcr *pcr) in rts5264_init_params() argument
843 struct rtsx_cr_option *option = &pcr->option; in rts5264_init_params()
844 struct rtsx_hw_param *hw_param = &pcr->hw_param; in rts5264_init_params()
847 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5264_init_params()
848 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rts5264_init_params()
849 rtsx_pci_read_register(pcr, RTS5264_FW_STATUS, &val); in rts5264_init_params()
851 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; in rts5264_init_params()
852 pcr->num_slots = 1; in rts5264_init_params()
853 pcr->ops = &rts5264_pcr_ops; in rts5264_init_params()
855 pcr->flags = 0; in rts5264_init_params()
856 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5264_init_params()
857 pcr->sd30_drive_sel_1v8 = 0x00; in rts5264_init_params()
858 pcr->sd30_drive_sel_3v3 = 0x00; in rts5264_init_params()
859 pcr->aspm_en = ASPM_L1_EN; in rts5264_init_params()
860 pcr->aspm_mode = ASPM_MODE_REG; in rts5264_init_params()
861 pcr->tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11); in rts5264_init_params()
862 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5264_init_params()
864 pcr->ic_version = rts5264_get_ic_version(pcr); in rts5264_init_params()
865 pcr->sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl; in rts5264_init_params()
866 pcr->sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl; in rts5264_init_params()
868 pcr->reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3; in rts5264_init_params()