Lines Matching defs:msdc_host
448 struct msdc_host { struct
449 struct device *dev;
450 const struct mtk_mmc_compatible *dev_comp;
451 int cmd_rsp;
453 spinlock_t lock;
454 struct mmc_request *mrq;
455 struct mmc_command *cmd;
456 struct mmc_data *data;
457 int error;
459 void __iomem *base; /* host base address */
460 void __iomem *top_base; /* host top register base address */
462 struct msdc_dma dma; /* dma channel */
463 u64 dma_mask;
465 u32 timeout_ns; /* data timeout ns */
466 u32 timeout_clks; /* data timeout clks */
468 struct pinctrl *pinctrl;
469 struct pinctrl_state *pins_default;
470 struct pinctrl_state *pins_uhs;
471 struct pinctrl_state *pins_eint;
472 struct delayed_work req_timeout;
473 int irq; /* host interrupt */
474 int eint_irq; /* interrupt from sdio device for waking up system */
475 struct reset_control *reset;
477 struct clk *src_clk; /* msdc source clock */
478 struct clk *h_clk; /* msdc h_clk */
479 struct clk *bus_clk; /* bus clock which used to access register */
480 struct clk *src_clk_cg; /* msdc source clock control gate */
481 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
482 struct clk *crypto_clk; /* msdc crypto clock control gate */
483 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
484 u32 mclk; /* mmc subsystem clock frequency */
485 u32 src_clk_freq; /* source clock frequency */
486 unsigned char timing;
487 bool vqmmc_enabled;
488 u32 latch_ck;
489 u32 hs400_ds_delay;
490 u32 hs400_ds_dly3;
491 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
492 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
493 u32 tuning_step;
494 bool hs400_cmd_resp_sel_rising;
496 bool hs400_mode; /* current eMMC will run at hs400 mode */
497 bool hs400_tuning; /* hs400 mode online tuning */
498 bool internal_cd; /* Use internal card-detect logic */
499 bool cqhci; /* support eMMC hw cmdq */
500 bool hsq_en; /* Host Software Queue is enabled */
501 struct msdc_save_para save_para; /* used when gate HCLK */
502 struct msdc_tune_para def_tune_para; /* default tune setting */
503 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
504 struct cqhci_host *cq_host;
505 u32 cq_ssc1_time;