28 	struct rtsx_pcr		*pcr;  member
58 	rtsx_pci_write_register(host->pcr, CARD_STOP,  in sd_clear_error()
75 			rtsx_pci_read_register(host->pcr, start + i + j,  in dump_reg_range()
93 	return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;  in sd_get_cd_int()
96 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)  in sd_cmd_set_sd_cmd()  argument
98 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,  in sd_cmd_set_sd_cmd()
100 	rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);  in sd_cmd_set_sd_cmd()
103 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)  in sd_cmd_set_data_len()  argument
105 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);  in sd_cmd_set_data_len()
106 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);  in sd_cmd_set_data_len()
107 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);  in sd_cmd_set_data_len()
108 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);  in sd_cmd_set_data_len()
149 	struct rtsx_pcr *pcr = host->pcr;  in sd_pre_dma_transfer()  local
162 		count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);  in sd_pre_dma_transfer()
200 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_post_req()  local
204 	rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);  in sdmmc_post_req()
211 	struct rtsx_pcr *pcr = host->pcr;  in sd_send_cmd_get_rsp()  local
235 		err = rtsx_pci_write_register(pcr, SD_BUS_STAT,  in sd_send_cmd_get_rsp()
243 	rtsx_pci_init_cmd(pcr);  in sd_send_cmd_get_rsp()
244 	sd_cmd_set_sd_cmd(pcr, cmd);  in sd_send_cmd_get_rsp()
245 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);  in sd_send_cmd_get_rsp()
246 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,  in sd_send_cmd_get_rsp()
248 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,  in sd_send_cmd_get_rsp()
250 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,  in sd_send_cmd_get_rsp()
257 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);  in sd_send_cmd_get_rsp()
261 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);  in sd_send_cmd_get_rsp()
264 	rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);  in sd_send_cmd_get_rsp()
266 	err = rtsx_pci_send_cmd(pcr, timeout);  in sd_send_cmd_get_rsp()
281 	ptr = rtsx_pci_get_cmd_data(pcr) + 1;  in sd_send_cmd_get_rsp()
322 		rtsx_pci_write_register(pcr, SD_BUS_STAT,  in sd_send_cmd_get_rsp()
329 	struct rtsx_pcr *pcr = host->pcr;  in sd_read_data()  local
344 	rtsx_pci_init_cmd(pcr);  in sd_read_data()
345 	sd_cmd_set_sd_cmd(pcr, cmd);  in sd_read_data()
346 	sd_cmd_set_data_len(pcr, 1, byte_cnt);  in sd_read_data()
347 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,  in sd_read_data()
351 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in sd_read_data()
354 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,  in sd_read_data()
356 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,  in sd_read_data()
359 	err = rtsx_pci_send_cmd(pcr, timeout);  in sd_read_data()
368 		err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);  in sd_read_data()
383 	struct rtsx_pcr *pcr = host->pcr;  in sd_write_data()  local
397 		err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);  in sd_write_data()
405 	rtsx_pci_init_cmd(pcr);  in sd_write_data()
406 	sd_cmd_set_data_len(pcr, 1, byte_cnt);  in sd_write_data()
407 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,  in sd_write_data()
410 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,  in sd_write_data()
412 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,  in sd_write_data()
415 	err = rtsx_pci_send_cmd(pcr, timeout);  in sd_write_data()
429 	struct rtsx_pcr *pcr = host->pcr;  in sd_read_long_data()  local
450 	rtsx_pci_init_cmd(pcr);  in sd_read_long_data()
451 	sd_cmd_set_sd_cmd(pcr, cmd);  in sd_read_long_data()
452 	sd_cmd_set_data_len(pcr, data->blocks, data->blksz);  in sd_read_long_data()
453 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in sd_read_long_data()
455 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,  in sd_read_long_data()
457 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,  in sd_read_long_data()
459 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,  in sd_read_long_data()
461 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);  in sd_read_long_data()
462 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,  in sd_read_long_data()
465 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,  in sd_read_long_data()
467 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);  in sd_read_long_data()
468 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,  in sd_read_long_data()
470 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,  in sd_read_long_data()
472 	rtsx_pci_send_cmd_no_wait(pcr);  in sd_read_long_data()
474 	err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);  in sd_read_long_data()
487 	struct rtsx_pcr *pcr = host->pcr;  in sd_write_long_data()  local
510 	rtsx_pci_init_cmd(pcr);  in sd_write_long_data()
511 	sd_cmd_set_data_len(pcr, data->blocks, data->blksz);  in sd_write_long_data()
512 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in sd_write_long_data()
514 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,  in sd_write_long_data()
516 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,  in sd_write_long_data()
518 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,  in sd_write_long_data()
520 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);  in sd_write_long_data()
521 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,  in sd_write_long_data()
524 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,  in sd_write_long_data()
526 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);  in sd_write_long_data()
527 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,  in sd_write_long_data()
529 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,  in sd_write_long_data()
531 	rtsx_pci_send_cmd_no_wait(pcr);  in sd_write_long_data()
532 	err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);  in sd_write_long_data()
543 	rtsx_pci_write_register(host->pcr, SD_CFG1,  in sd_enable_initial_mode()
549 	rtsx_pci_write_register(host->pcr, SD_CFG1,  in sd_disable_initial_mode()
617 	struct rtsx_pcr *pcr = host->pcr;  in sd_change_phase()  local
622 	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);  in sd_change_phase()
625 		rtsx_pci_write_register(pcr, SD_VPRX_CTL,  in sd_change_phase()
629 		rtsx_pci_write_register(pcr, SD_VPTX_CTL,  in sd_change_phase()
632 	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);  in sd_change_phase()
633 	rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,  in sd_change_phase()
635 	rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);  in sd_change_phase()
636 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);  in sd_change_phase()
691 		rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);  in sd_wait_data_idle()
704 	struct rtsx_pcr *pcr = host->pcr;  in sd_tuning_rx_cmd()  local
708 	rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,  in sd_tuning_rx_cmd()
717 		rtsx_pci_write_register(pcr, SD_CFG3,  in sd_tuning_rx_cmd()
722 	rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);  in sd_tuning_rx_cmd()
799 	struct rtsx_pcr *pcr = host->pcr;  in sd_request()  local
814 	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);  in sd_request()
820 	mutex_lock(&pcr->pcr_mutex);  in sd_request()
822 	rtsx_pci_start_run(pcr);  in sd_request()
824 	rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,  in sd_request()
826 	rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);  in sd_request()
827 	rtsx_pci_write_register(pcr, CARD_SHARE_MODE,  in sd_request()
857 	mutex_unlock(&pcr->pcr_mutex);  in sd_request()
898 		err = rtsx_pci_write_register(host->pcr, SD_CFG1,  in sd_set_bus_width()
906 	struct rtsx_pcr *pcr = host->pcr;  in sd_power_on()  local
916 		rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);  in sd_power_on()
922 	rtsx_pci_init_cmd(pcr);  in sd_power_on()
923 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);  in sd_power_on()
924 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,  in sd_power_on()
926 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,  in sd_power_on()
928 	err = rtsx_pci_send_cmd(pcr, 100);  in sd_power_on()
932 	err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);  in sd_power_on()
936 	err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);  in sd_power_on()
942 	err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);  in sd_power_on()
947 	rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);  in sd_power_on()
949 	if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {  in sd_power_on()
954 		rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);  in sd_power_on()
959 		if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)  in sd_power_on()
966 		val = rtsx_pci_readl(pcr, RTSX_BIPR);  in sd_power_on()
968 			pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;  in sd_power_on()
980 	struct rtsx_pcr *pcr = host->pcr;  in sd_power_off()  local
985 	rtsx_pci_init_cmd(pcr);  in sd_power_off()
987 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);  in sd_power_off()
988 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);  in sd_power_off()
990 	err = rtsx_pci_send_cmd(pcr, 100);  in sd_power_off()
994 	err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);  in sd_power_off()
998 	return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);  in sd_power_off()
1016 	struct rtsx_pcr *pcr = host->pcr;  in sd_set_timing()  local
1019 	rtsx_pci_init_cmd(pcr);  in sd_set_timing()
1024 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,  in sd_set_timing()
1027 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in sd_set_timing()
1029 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,  in sd_set_timing()
1031 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);  in sd_set_timing()
1036 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,  in sd_set_timing()
1039 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in sd_set_timing()
1041 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,  in sd_set_timing()
1043 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);  in sd_set_timing()
1044 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,  in sd_set_timing()
1046 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,  in sd_set_timing()
1053 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,  in sd_set_timing()
1055 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in sd_set_timing()
1057 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,  in sd_set_timing()
1059 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);  in sd_set_timing()
1060 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,  in sd_set_timing()
1062 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,  in sd_set_timing()
1067 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in sd_set_timing()
1069 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in sd_set_timing()
1071 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,  in sd_set_timing()
1073 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);  in sd_set_timing()
1074 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in sd_set_timing()
1076 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,  in sd_set_timing()
1081 	err = rtsx_pci_send_cmd(pcr, 100);  in sd_set_timing()
1089 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_set_ios()  local
1094 	if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))  in sdmmc_set_ios()
1097 	mutex_lock(&pcr->pcr_mutex);  in sdmmc_set_ios()
1099 	rtsx_pci_start_run(pcr);  in sdmmc_set_ios()
1128 	rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,  in sdmmc_set_ios()
1131 	mutex_unlock(&pcr->pcr_mutex);  in sdmmc_set_ios()
1137 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_get_ro()  local
1144 	mutex_lock(&pcr->pcr_mutex);  in sdmmc_get_ro()
1146 	rtsx_pci_start_run(pcr);  in sdmmc_get_ro()
1149 	val = rtsx_pci_readl(pcr, RTSX_BIPR);  in sdmmc_get_ro()
1154 	mutex_unlock(&pcr->pcr_mutex);  in sdmmc_get_ro()
1162 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_get_cd()  local
1169 	mutex_lock(&pcr->pcr_mutex);  in sdmmc_get_cd()
1171 	rtsx_pci_start_run(pcr);  in sdmmc_get_cd()
1174 	val = rtsx_pci_card_exist(pcr);  in sdmmc_get_cd()
1179 	mutex_unlock(&pcr->pcr_mutex);  in sdmmc_get_cd()
1186 	struct rtsx_pcr *pcr = host->pcr;  in sd_wait_voltage_stable_1()  local
1200 	err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);  in sd_wait_voltage_stable_1()
1209 	err = rtsx_pci_write_register(pcr, SD_BUS_STAT,  in sd_wait_voltage_stable_1()
1219 	struct rtsx_pcr *pcr = host->pcr;  in sd_wait_voltage_stable_2()  local
1227 	err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);  in sd_wait_voltage_stable_2()
1237 	err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);  in sd_wait_voltage_stable_2()
1248 		rtsx_pci_write_register(pcr, SD_BUS_STAT,  in sd_wait_voltage_stable_2()
1250 		rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);  in sd_wait_voltage_stable_2()
1260 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_switch_voltage()  local
1270 	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);  in sdmmc_switch_voltage()
1274 	mutex_lock(&pcr->pcr_mutex);  in sdmmc_switch_voltage()
1276 	rtsx_pci_start_run(pcr);  in sdmmc_switch_voltage()
1289 	err = rtsx_pci_switch_output_voltage(pcr, voltage);  in sdmmc_switch_voltage()
1301 	err = rtsx_pci_write_register(pcr, SD_BUS_STAT,  in sdmmc_switch_voltage()
1304 	mutex_unlock(&pcr->pcr_mutex);  in sdmmc_switch_voltage()
1312 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_execute_tuning()  local
1318 	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);  in sdmmc_execute_tuning()
1322 	mutex_lock(&pcr->pcr_mutex);  in sdmmc_execute_tuning()
1324 	rtsx_pci_start_run(pcr);  in sdmmc_execute_tuning()
1329 		err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);  in sdmmc_execute_tuning()
1333 		err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);  in sdmmc_execute_tuning()
1337 		err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);  in sdmmc_execute_tuning()
1352 		err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);  in sdmmc_execute_tuning()
1355 	mutex_unlock(&pcr->pcr_mutex);  in sdmmc_execute_tuning()
1364 	struct rtsx_pcr *pcr = host->pcr;  in sdmmc_init_sd_express()  local
1366 	if (PCI_PID(pcr) == PID_5264) {  in sdmmc_init_sd_express()
1367 		pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2,  in sdmmc_init_sd_express()
1369 		pci_write_config_byte(pcr->pci, 0x80e, 0x02);  in sdmmc_init_sd_express()
1370 		pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2,  in sdmmc_init_sd_express()
1377 	rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);  in sdmmc_init_sd_express()
1378 	rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);  in sdmmc_init_sd_express()
1379 	rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);  in sdmmc_init_sd_express()
1381 	rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);  in sdmmc_init_sd_express()
1382 	rtsx_pci_write_register(pcr, LDO_VCC_CFG0,  in sdmmc_init_sd_express()
1384 		pcr->option.sd_800mA_ocp_thd);  in sdmmc_init_sd_express()
1386 	if (pcr->ops->disable_auto_blink)  in sdmmc_init_sd_express()
1387 		pcr->ops->disable_auto_blink(pcr);  in sdmmc_init_sd_express()
1389 	if (PCI_PID(pcr) == PID_5264) {  in sdmmc_init_sd_express()
1390 		rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,  in sdmmc_init_sd_express()
1392 		rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);  in sdmmc_init_sd_express()
1396 	pcr->hw_param.interrupt_en &= ~(SD_INT_EN);  in sdmmc_init_sd_express()
1397 	rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);  in sdmmc_init_sd_express()
1399 	rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,  in sdmmc_init_sd_express()
1401 	rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,  in sdmmc_init_sd_express()
1403 	rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,  in sdmmc_init_sd_express()
1405 	rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,  in sdmmc_init_sd_express()
1428 	struct rtsx_pcr *pcr = host->pcr;  in init_extra_caps()  local
1430 	dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);  in init_extra_caps()
1432 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)  in init_extra_caps()
1434 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)  in init_extra_caps()
1436 	if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)  in init_extra_caps()
1438 	if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)  in init_extra_caps()
1440 	if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)  in init_extra_caps()
1442 	if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)  in init_extra_caps()
1444 	if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)  in init_extra_caps()
1451 	struct rtsx_pcr *pcr = host->pcr;  in realtek_init_host()  local
1459 	if (pcr->rtd3_en)  in realtek_init_host()
1488 	struct rtsx_pcr *pcr;  in rtsx_pci_sdmmc_drv_probe()  local
1495 	pcr = handle->pcr;  in rtsx_pci_sdmmc_drv_probe()
1496 	if (!pcr)  in rtsx_pci_sdmmc_drv_probe()
1506 	host->pcr = pcr;  in rtsx_pci_sdmmc_drv_probe()
1514 	pcr->slots[RTSX_SD_CARD].p_dev = pdev;  in rtsx_pci_sdmmc_drv_probe()
1515 	pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;  in rtsx_pci_sdmmc_drv_probe()
1542 	struct rtsx_pcr *pcr;  in rtsx_pci_sdmmc_drv_remove()  local
1545 	pcr = host->pcr;  in rtsx_pci_sdmmc_drv_remove()
1546 	pcr->slots[RTSX_SD_CARD].p_dev = NULL;  in rtsx_pci_sdmmc_drv_remove()
1547 	pcr->slots[RTSX_SD_CARD].card_event = NULL;  in rtsx_pci_sdmmc_drv_remove()
1558 		rtsx_pci_complete_unfinished_transfer(pcr);  in rtsx_pci_sdmmc_drv_remove()