83 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
86 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
205  * met at 25MHz for Default Speed mode, those controllers work at
206  * 19MHz instead
403 		 * requirements met at 25MHz for Default Speed mode,  in sdhci_arasan_set_clock()
404 		 * those controllers work at 19MHz instead.  in sdhci_arasan_set_clock()
769 		/* For 50MHz clock, 30 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
773 		/* For 100MHz clock, 15 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
778 		/* For 200MHz clock, 8 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
838 		/* For 50MHz clock, 120 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
842 		/* For 100MHz clock, 60 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
843 		tap_max = 60;  in sdhci_zynqmp_sampleclk_set_phase()
847 		/* For 200MHz clock, 30 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
898 		/* For 50MHz clock, 30 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
902 		/* For 100MHz clock, 15 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
907 		/* For 200MHz clock, 8 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
965 		/* For 50MHz clock, 120 Taps are available */  in sdhci_versal_sampleclk_set_phase()
969 		/* For 100MHz clock, 60 Taps are available */  in sdhci_versal_sampleclk_set_phase()
970 		tap_max = 60;  in sdhci_versal_sampleclk_set_phase()
974 		/* For 200MHz clock, 30 Taps are available */  in sdhci_versal_sampleclk_set_phase()
1023 		 /* For 200MHz clock, 32 Taps are available */  in sdhci_versal_net_emmc_sdcardclk_set_phase()
1189  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
1207 	u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()  local
1220 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()
1757 	u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;  in sdhci_zynqmp_set_dynamic_config()  local
1781 	mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_zynqmp_set_dynamic_config()
1782 	if (mhz > 100 && mhz <= 200)  in sdhci_zynqmp_set_dynamic_config()
1783 		mhz = 200;  in sdhci_zynqmp_set_dynamic_config()
1784 	else if (mhz > 50 && mhz <= 100)  in sdhci_zynqmp_set_dynamic_config()
1785 		mhz = 100;  in sdhci_zynqmp_set_dynamic_config()
1786 	else if (mhz > 25 && mhz <= 50)  in sdhci_zynqmp_set_dynamic_config()
1787 		mhz = 50;  in sdhci_zynqmp_set_dynamic_config()
1789 		mhz = 25;  in sdhci_zynqmp_set_dynamic_config()
1791 	ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);  in sdhci_zynqmp_set_dynamic_config()