Lines Matching full:host
43 #include <linux/mmc/host.h>
255 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) argument
257 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, in sh_mmcif_bitset() argument
260 writel(val | readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitset()
263 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, in sh_mmcif_bitclr() argument
266 writel(~val & readl(host->addr + reg), host->addr + reg); in sh_mmcif_bitclr()
271 struct sh_mmcif_host *host = arg; in sh_mmcif_dma_complete() local
272 struct mmc_request *mrq = host->mrq; in sh_mmcif_dma_complete()
273 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_dma_complete()
281 complete(&host->dma_complete); in sh_mmcif_dma_complete()
284 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_rx() argument
286 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_rx()
289 struct dma_chan *chan = host->chan_rx; in sh_mmcif_start_dma_rx()
290 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_rx()
297 host->dma_active = true; in sh_mmcif_start_dma_rx()
304 desc->callback_param = host; in sh_mmcif_start_dma_rx()
306 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); in sh_mmcif_start_dma_rx()
316 host->chan_rx = NULL; in sh_mmcif_start_dma_rx()
317 host->dma_active = false; in sh_mmcif_start_dma_rx()
320 chan = host->chan_tx; in sh_mmcif_start_dma_rx()
322 host->chan_tx = NULL; in sh_mmcif_start_dma_rx()
327 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_rx()
334 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) in sh_mmcif_start_dma_tx() argument
336 struct mmc_data *data = host->mrq->data; in sh_mmcif_start_dma_tx()
339 struct dma_chan *chan = host->chan_tx; in sh_mmcif_start_dma_tx()
340 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_start_dma_tx()
347 host->dma_active = true; in sh_mmcif_start_dma_tx()
354 desc->callback_param = host; in sh_mmcif_start_dma_tx()
356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
366 host->chan_tx = NULL; in sh_mmcif_start_dma_tx()
367 host->dma_active = false; in sh_mmcif_start_dma_tx()
370 chan = host->chan_rx; in sh_mmcif_start_dma_tx()
372 host->chan_rx = NULL; in sh_mmcif_start_dma_tx()
377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_start_dma_tx()
385 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) in sh_mmcif_request_dma_pdata() argument
397 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, in sh_mmcif_dma_slave_config() argument
404 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); in sh_mmcif_dma_slave_config()
421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) in sh_mmcif_request_dma() argument
423 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request_dma()
424 host->dma_active = false; in sh_mmcif_request_dma()
430 host->chan_tx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
432 host->chan_rx = sh_mmcif_request_dma_pdata(host, in sh_mmcif_request_dma()
435 host->chan_tx = dma_request_chan(dev, "tx"); in sh_mmcif_request_dma()
436 if (IS_ERR(host->chan_tx)) in sh_mmcif_request_dma()
437 host->chan_tx = NULL; in sh_mmcif_request_dma()
438 host->chan_rx = dma_request_chan(dev, "rx"); in sh_mmcif_request_dma()
439 if (IS_ERR(host->chan_rx)) in sh_mmcif_request_dma()
440 host->chan_rx = NULL; in sh_mmcif_request_dma()
443 if (!host->chan_tx || !host->chan_rx || in sh_mmcif_request_dma()
444 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || in sh_mmcif_request_dma()
445 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) in sh_mmcif_request_dma()
448 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, in sh_mmcif_request_dma()
449 host->chan_rx); in sh_mmcif_request_dma()
454 if (host->chan_tx) in sh_mmcif_request_dma()
455 dma_release_channel(host->chan_tx); in sh_mmcif_request_dma()
456 if (host->chan_rx) in sh_mmcif_request_dma()
457 dma_release_channel(host->chan_rx); in sh_mmcif_request_dma()
458 host->chan_tx = host->chan_rx = NULL; in sh_mmcif_request_dma()
461 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) in sh_mmcif_release_dma() argument
463 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); in sh_mmcif_release_dma()
465 if (host->chan_tx) { in sh_mmcif_release_dma()
466 struct dma_chan *chan = host->chan_tx; in sh_mmcif_release_dma()
467 host->chan_tx = NULL; in sh_mmcif_release_dma()
470 if (host->chan_rx) { in sh_mmcif_release_dma()
471 struct dma_chan *chan = host->chan_rx; in sh_mmcif_release_dma()
472 host->chan_rx = NULL; in sh_mmcif_release_dma()
476 host->dma_active = false; in sh_mmcif_release_dma()
479 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) in sh_mmcif_clock_control() argument
481 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clock_control()
484 unsigned int current_clk = clk_get_rate(host->clk); in sh_mmcif_clock_control()
487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
488 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); in sh_mmcif_clock_control()
493 if (host->clkdiv_map) { in sh_mmcif_clock_control()
501 if (!((1 << i) & host->clkdiv_map)) in sh_mmcif_clock_control()
510 freq = clk_round_rate(host->clk, clk * div); in sh_mmcif_clock_control()
524 clk_set_rate(host->clk, best_freq); in sh_mmcif_clock_control()
532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
533 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); in sh_mmcif_clock_control()
536 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) in sh_mmcif_sync_reset() argument
540 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); in sh_mmcif_sync_reset()
542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); in sh_mmcif_sync_reset()
543 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); in sh_mmcif_sync_reset()
544 if (host->ccs_enable) in sh_mmcif_sync_reset()
546 if (host->clk_ctrl2_enable) in sh_mmcif_sync_reset()
547 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); in sh_mmcif_sync_reset()
548 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | in sh_mmcif_sync_reset()
551 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); in sh_mmcif_sync_reset()
554 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) in sh_mmcif_error_manage() argument
556 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_error_manage()
560 host->sd_error = false; in sh_mmcif_error_manage()
562 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); in sh_mmcif_error_manage()
563 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); in sh_mmcif_error_manage()
568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); in sh_mmcif_error_manage()
569 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); in sh_mmcif_error_manage()
571 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) in sh_mmcif_error_manage()
581 sh_mmcif_sync_reset(host); in sh_mmcif_error_manage()
588 host->state, host->wait_for); in sh_mmcif_error_manage()
592 host->state, host->wait_for); in sh_mmcif_error_manage()
596 host->state, host->wait_for); in sh_mmcif_error_manage()
602 static void sh_mmcif_single_read(struct sh_mmcif_host *host, in sh_mmcif_single_read() argument
607 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_read()
610 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, in sh_mmcif_single_read()
613 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
616 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_single_read()
619 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) in sh_mmcif_read_block() argument
621 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_read_block()
622 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_read_block()
623 struct mmc_data *data = host->mrq->data; in sh_mmcif_read_block()
627 if (host->sd_error) { in sh_mmcif_read_block()
629 data->error = sh_mmcif_error_manage(host); in sh_mmcif_read_block()
642 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_read_block()
643 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_read_block()
645 sg_miter_stop(&host->sg_miter); in sh_mmcif_read_block()
648 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); in sh_mmcif_read_block()
649 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
654 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, in sh_mmcif_multi_read() argument
657 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_multi_read()
663 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_read()
675 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
677 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_multi_read()
680 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) in sh_mmcif_mread_block() argument
682 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_mread_block()
683 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mread_block()
684 struct mmc_data *data = host->mrq->data; in sh_mmcif_mread_block()
688 if (host->sd_error) { in sh_mmcif_mread_block()
690 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mread_block()
697 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mread_block()
698 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); in sh_mmcif_mread_block()
700 sgm->consumed = host->blocksize; in sh_mmcif_mread_block()
702 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); in sh_mmcif_mread_block()
712 static void sh_mmcif_single_write(struct sh_mmcif_host *host, in sh_mmcif_single_write() argument
717 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_single_write()
720 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, in sh_mmcif_single_write()
723 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
726 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_single_write()
729 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) in sh_mmcif_write_block() argument
731 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_write_block()
732 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_write_block()
733 struct mmc_data *data = host->mrq->data; in sh_mmcif_write_block()
737 if (host->sd_error) { in sh_mmcif_write_block()
739 data->error = sh_mmcif_error_manage(host); in sh_mmcif_write_block()
752 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_write_block()
753 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_write_block()
755 sg_miter_stop(&host->sg_miter); in sh_mmcif_write_block()
758 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); in sh_mmcif_write_block()
759 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
764 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, in sh_mmcif_multi_write() argument
767 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_multi_write()
773 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & in sh_mmcif_multi_write()
785 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
787 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_multi_write()
790 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) in sh_mmcif_mwrite_block() argument
792 struct sg_mapping_iter *sgm = &host->sg_miter; in sh_mmcif_mwrite_block()
793 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_mwrite_block()
794 struct mmc_data *data = host->mrq->data; in sh_mmcif_mwrite_block()
798 if (host->sd_error) { in sh_mmcif_mwrite_block()
800 data->error = sh_mmcif_error_manage(host); in sh_mmcif_mwrite_block()
807 for (i = 0; i < host->blocksize / 4; i++) in sh_mmcif_mwrite_block()
808 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); in sh_mmcif_mwrite_block()
810 sgm->consumed = host->blocksize; in sh_mmcif_mwrite_block()
817 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); in sh_mmcif_mwrite_block()
822 static void sh_mmcif_get_response(struct sh_mmcif_host *host, in sh_mmcif_get_response() argument
826 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); in sh_mmcif_get_response()
827 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); in sh_mmcif_get_response()
828 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); in sh_mmcif_get_response()
829 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
831 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); in sh_mmcif_get_response()
834 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, in sh_mmcif_get_cmd12response() argument
837 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); in sh_mmcif_get_cmd12response()
840 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, in sh_mmcif_set_cmd() argument
843 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_cmd()
872 switch (host->bus_width) { in sh_mmcif_set_cmd()
886 switch (host->timing) { in sh_mmcif_set_cmd()
889 * MMC core will only set this timing, if the host in sh_mmcif_set_cmd()
905 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, in sh_mmcif_set_cmd()
923 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, in sh_mmcif_data_trans() argument
926 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_data_trans()
930 sh_mmcif_multi_read(host, mrq); in sh_mmcif_data_trans()
933 sh_mmcif_multi_write(host, mrq); in sh_mmcif_data_trans()
936 sh_mmcif_single_write(host, mrq); in sh_mmcif_data_trans()
940 sh_mmcif_single_read(host, mrq); in sh_mmcif_data_trans()
948 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, in sh_mmcif_start_cmd() argument
961 if (host->ccs_enable) in sh_mmcif_start_cmd()
965 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); in sh_mmcif_start_cmd()
966 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, in sh_mmcif_start_cmd()
969 opc = sh_mmcif_set_cmd(host, mrq); in sh_mmcif_start_cmd()
971 if (host->ccs_enable) in sh_mmcif_start_cmd()
972 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); in sh_mmcif_start_cmd()
974 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); in sh_mmcif_start_cmd()
975 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); in sh_mmcif_start_cmd()
977 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); in sh_mmcif_start_cmd()
979 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_start_cmd()
980 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); in sh_mmcif_start_cmd()
982 host->wait_for = MMCIF_WAIT_FOR_CMD; in sh_mmcif_start_cmd()
983 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_start_cmd()
984 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_start_cmd()
987 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, in sh_mmcif_stop_cmd() argument
990 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_stop_cmd()
994 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); in sh_mmcif_stop_cmd()
997 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); in sh_mmcif_stop_cmd()
1001 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_stop_cmd()
1005 host->wait_for = MMCIF_WAIT_FOR_STOP; in sh_mmcif_stop_cmd()
1010 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_request() local
1011 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_request()
1014 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_request()
1015 if (host->state != STATE_IDLE) { in sh_mmcif_request()
1017 __func__, host->state); in sh_mmcif_request()
1018 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1024 host->state = STATE_REQUEST; in sh_mmcif_request()
1025 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_request()
1027 host->mrq = mrq; in sh_mmcif_request()
1029 sh_mmcif_start_cmd(host, mrq); in sh_mmcif_request()
1032 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) in sh_mmcif_clk_setup() argument
1034 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_clk_setup()
1036 if (host->mmc->f_max) { in sh_mmcif_clk_setup()
1039 f_max = host->mmc->f_max; in sh_mmcif_clk_setup()
1041 f_min = clk_round_rate(host->clk, f_min_old / 2); in sh_mmcif_clk_setup()
1050 host->clkdiv_map = 0x3ff; in sh_mmcif_clk_setup()
1052 host->mmc->f_max = f_max >> ffs(host->clkdiv_map); in sh_mmcif_clk_setup()
1053 host->mmc->f_min = f_min >> fls(host->clkdiv_map); in sh_mmcif_clk_setup()
1055 unsigned int clk = clk_get_rate(host->clk); in sh_mmcif_clk_setup()
1057 host->mmc->f_max = clk / 2; in sh_mmcif_clk_setup()
1058 host->mmc->f_min = clk / 512; in sh_mmcif_clk_setup()
1062 host->mmc->f_max, host->mmc->f_min); in sh_mmcif_clk_setup()
1067 struct sh_mmcif_host *host = mmc_priv(mmc); in sh_mmcif_set_ios() local
1068 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_set_ios()
1071 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_set_ios()
1072 if (host->state != STATE_IDLE) { in sh_mmcif_set_ios()
1074 __func__, host->state); in sh_mmcif_set_ios()
1075 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1079 host->state = STATE_IOS; in sh_mmcif_set_ios()
1080 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_set_ios()
1086 if (!host->power) { in sh_mmcif_set_ios()
1087 clk_prepare_enable(host->clk); in sh_mmcif_set_ios()
1089 sh_mmcif_sync_reset(host); in sh_mmcif_set_ios()
1090 sh_mmcif_request_dma(host); in sh_mmcif_set_ios()
1091 host->power = true; in sh_mmcif_set_ios()
1097 if (host->power) { in sh_mmcif_set_ios()
1098 sh_mmcif_clock_control(host, 0); in sh_mmcif_set_ios()
1099 sh_mmcif_release_dma(host); in sh_mmcif_set_ios()
1101 clk_disable_unprepare(host->clk); in sh_mmcif_set_ios()
1102 host->power = false; in sh_mmcif_set_ios()
1106 sh_mmcif_clock_control(host, ios->clock); in sh_mmcif_set_ios()
1110 host->timing = ios->timing; in sh_mmcif_set_ios()
1111 host->bus_width = ios->bus_width; in sh_mmcif_set_ios()
1112 host->state = STATE_IDLE; in sh_mmcif_set_ios()
1121 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) in sh_mmcif_end_cmd() argument
1123 struct mmc_command *cmd = host->mrq->cmd; in sh_mmcif_end_cmd()
1124 struct mmc_data *data = host->mrq->data; in sh_mmcif_end_cmd()
1125 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_end_cmd()
1128 if (host->sd_error) { in sh_mmcif_end_cmd()
1136 cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1141 host->sd_error = false; in sh_mmcif_end_cmd()
1149 sh_mmcif_get_response(host, cmd); in sh_mmcif_end_cmd()
1158 init_completion(&host->dma_complete); in sh_mmcif_end_cmd()
1161 if (host->chan_rx) in sh_mmcif_end_cmd()
1162 sh_mmcif_start_dma_rx(host); in sh_mmcif_end_cmd()
1164 if (host->chan_tx) in sh_mmcif_end_cmd()
1165 sh_mmcif_start_dma_tx(host); in sh_mmcif_end_cmd()
1168 if (!host->dma_active) { in sh_mmcif_end_cmd()
1169 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); in sh_mmcif_end_cmd()
1174 time = wait_for_completion_interruptible_timeout(&host->dma_complete, in sh_mmcif_end_cmd()
1175 host->timeout); in sh_mmcif_end_cmd()
1178 dma_unmap_sg(host->chan_rx->device->dev, in sh_mmcif_end_cmd()
1182 dma_unmap_sg(host->chan_tx->device->dev, in sh_mmcif_end_cmd()
1186 if (host->sd_error) { in sh_mmcif_end_cmd()
1187 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1190 data->error = sh_mmcif_error_manage(host); in sh_mmcif_end_cmd()
1192 dev_err(host->mmc->parent, "DMA timeout!\n"); in sh_mmcif_end_cmd()
1195 dev_err(host->mmc->parent, in sh_mmcif_end_cmd()
1199 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, in sh_mmcif_end_cmd()
1201 host->dma_active = false; in sh_mmcif_end_cmd()
1207 dmaengine_terminate_sync(host->chan_rx); in sh_mmcif_end_cmd()
1209 dmaengine_terminate_sync(host->chan_tx); in sh_mmcif_end_cmd()
1217 struct sh_mmcif_host *host = dev_id; in sh_mmcif_irqt() local
1219 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_irqt()
1224 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_irqt()
1225 wait_work = host->wait_for; in sh_mmcif_irqt()
1226 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_irqt()
1228 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_irqt()
1230 mutex_lock(&host->thread_lock); in sh_mmcif_irqt()
1232 mrq = host->mrq; in sh_mmcif_irqt()
1235 host->state, host->wait_for); in sh_mmcif_irqt()
1236 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1247 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1251 wait = sh_mmcif_end_cmd(host); in sh_mmcif_irqt()
1255 wait = sh_mmcif_mread_block(host); in sh_mmcif_irqt()
1259 wait = sh_mmcif_read_block(host); in sh_mmcif_irqt()
1263 wait = sh_mmcif_mwrite_block(host); in sh_mmcif_irqt()
1267 wait = sh_mmcif_write_block(host); in sh_mmcif_irqt()
1270 if (host->sd_error) { in sh_mmcif_irqt()
1271 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1275 sh_mmcif_get_cmd12response(host, mrq->stop); in sh_mmcif_irqt()
1280 if (host->sd_error) { in sh_mmcif_irqt()
1281 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_irqt()
1290 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1292 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1296 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { in sh_mmcif_irqt()
1303 sh_mmcif_stop_cmd(host, mrq); in sh_mmcif_irqt()
1305 schedule_delayed_work(&host->timeout_work, host->timeout); in sh_mmcif_irqt()
1306 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1312 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_irqt()
1313 host->state = STATE_IDLE; in sh_mmcif_irqt()
1314 host->mrq = NULL; in sh_mmcif_irqt()
1315 mmc_request_done(host->mmc, mrq); in sh_mmcif_irqt()
1317 mutex_unlock(&host->thread_lock); in sh_mmcif_irqt()
1324 struct sh_mmcif_host *host = dev_id; in sh_mmcif_intr() local
1325 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_intr()
1328 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); in sh_mmcif_intr()
1329 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); in sh_mmcif_intr()
1330 if (host->ccs_enable) in sh_mmcif_intr()
1331 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); in sh_mmcif_intr()
1333 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); in sh_mmcif_intr()
1334 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); in sh_mmcif_intr()
1341 host->sd_error = true; in sh_mmcif_intr()
1345 if (!host->mrq) in sh_mmcif_intr()
1347 if (!host->dma_active) in sh_mmcif_intr()
1349 else if (host->sd_error) in sh_mmcif_intr()
1350 sh_mmcif_dma_complete(host); in sh_mmcif_intr()
1361 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); in sh_mmcif_timeout_work() local
1362 struct mmc_request *mrq = host->mrq; in sh_mmcif_timeout_work()
1363 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_timeout_work()
1366 if (host->dying) in sh_mmcif_timeout_work()
1370 spin_lock_irqsave(&host->lock, flags); in sh_mmcif_timeout_work()
1371 if (host->state == STATE_IDLE) { in sh_mmcif_timeout_work()
1372 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1377 host->wait_for, mrq->cmd->opcode); in sh_mmcif_timeout_work()
1379 host->state = STATE_TIMEOUT; in sh_mmcif_timeout_work()
1380 spin_unlock_irqrestore(&host->lock, flags); in sh_mmcif_timeout_work()
1386 switch (host->wait_for) { in sh_mmcif_timeout_work()
1388 mrq->cmd->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1391 mrq->stop->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1399 mrq->data->error = sh_mmcif_error_manage(host); in sh_mmcif_timeout_work()
1405 host->state = STATE_IDLE; in sh_mmcif_timeout_work()
1406 host->wait_for = MMCIF_WAIT_FOR_REQUEST; in sh_mmcif_timeout_work()
1407 host->mrq = NULL; in sh_mmcif_timeout_work()
1408 mmc_request_done(host->mmc, mrq); in sh_mmcif_timeout_work()
1411 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) in sh_mmcif_init_ocr() argument
1413 struct device *dev = sh_mmcif_host_to_dev(host); in sh_mmcif_init_ocr()
1415 struct mmc_host *mmc = host->mmc; in sh_mmcif_init_ocr()
1432 struct sh_mmcif_host *host; in sh_mmcif_probe() local
1455 host = mmc_priv(mmc); in sh_mmcif_probe()
1456 host->mmc = mmc; in sh_mmcif_probe()
1457 host->addr = reg; in sh_mmcif_probe()
1458 host->timeout = msecs_to_jiffies(10000); in sh_mmcif_probe()
1459 host->ccs_enable = true; in sh_mmcif_probe()
1460 host->clk_ctrl2_enable = false; in sh_mmcif_probe()
1462 host->pd = pdev; in sh_mmcif_probe()
1464 spin_lock_init(&host->lock); in sh_mmcif_probe()
1467 sh_mmcif_init_ocr(host); in sh_mmcif_probe()
1481 platform_set_drvdata(pdev, host); in sh_mmcif_probe()
1483 host->clk = devm_clk_get(dev, NULL); in sh_mmcif_probe()
1484 if (IS_ERR(host->clk)) { in sh_mmcif_probe()
1485 ret = PTR_ERR(host->clk); in sh_mmcif_probe()
1490 ret = clk_prepare_enable(host->clk); in sh_mmcif_probe()
1494 sh_mmcif_clk_setup(host); in sh_mmcif_probe()
1497 host->power = false; in sh_mmcif_probe()
1503 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); in sh_mmcif_probe()
1505 sh_mmcif_sync_reset(host); in sh_mmcif_probe()
1506 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_probe()
1510 sh_mmcif_irqt, 0, name, host); in sh_mmcif_probe()
1518 0, "sh_mmc:int", host); in sh_mmcif_probe()
1525 mutex_init(&host->thread_lock); in sh_mmcif_probe()
1534 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, in sh_mmcif_probe()
1535 clk_get_rate(host->clk) / 1000000UL); in sh_mmcif_probe()
1538 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1542 clk_disable_unprepare(host->clk); in sh_mmcif_probe()
1552 struct sh_mmcif_host *host = platform_get_drvdata(pdev); in sh_mmcif_remove() local
1554 host->dying = true; in sh_mmcif_remove()
1555 clk_prepare_enable(host->clk); in sh_mmcif_remove()
1560 mmc_remove_host(host->mmc); in sh_mmcif_remove()
1561 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_remove()
1568 cancel_delayed_work_sync(&host->timeout_work); in sh_mmcif_remove()
1570 clk_disable_unprepare(host->clk); in sh_mmcif_remove()
1571 mmc_free_host(host->mmc); in sh_mmcif_remove()
1579 struct sh_mmcif_host *host = dev_get_drvdata(dev); in sh_mmcif_suspend() local
1582 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); in sh_mmcif_suspend()