148 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_clear_spare()  local
152 		writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_clear_spare()
155 static inline void read_remaining_bytes(struct ma35_nand_info *nand, u32 *buf,  in read_remaining_bytes()  argument
158 	u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset);  in read_remaining_bytes()
170 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_read_spare()  local
176 		read_remaining_bytes(nand, buf, off, 4 - len, 1);  in ma35_read_spare()
182 		*buf++ = readl(nand->regs + MA35_NFI_REG_NANDRA0 + off + (i * 4));  in ma35_read_spare()
184 	read_remaining_bytes(nand, buf, off + (size & ~3), size % 4, 0);  in ma35_read_spare()
189 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_write_spare()  local
195 		writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j);  in ma35_write_spare()
200 		writel(*ptr, nand->regs + MA35_NFI_REG_NANDRA0 + j);  in ma35_write_spare()
204 		writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);  in ma35_write_spare()
208 		writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);  in ma35_write_spare()
217 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_target_enable()  local
222 		reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_target_enable()
223 		writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_target_enable()
225 		reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_target_enable()
227 		writel(reg, nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_target_enable()
234 static int ma35_nand_hwecc_init(struct nand_chip *chip, struct ma35_nand_info *nand)  in ma35_nand_hwecc_init()  argument
241 	nand->buffer = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);  in ma35_nand_hwecc_init()
242 	if (!nand->buffer)  in ma35_nand_hwecc_init()
246 	writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);  in ma35_nand_hwecc_init()
249 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_hwecc_init()
272 			dev_err(nand->dev, "ECC strength unsupported\n");  in ma35_nand_hwecc_init()
278 	writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_hwecc_init()
286 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nfi_correct()  local
304 		dev_err(nand->dev, "Invalid BCH_TSEL = 0x%lx\n",  in ma35_nfi_correct()
305 			readl(nand->regs + MA35_NFI_REG_NANDCTL) & BCH_MASK);  in ma35_nfi_correct()
317 		err_data[i] = readl(nand->regs + MA35_NFI_REG_NANDECCED0 + i * 4);  in ma35_nfi_correct()
334 		temp_addr[i * 2 + 0] = readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4)  in ma35_nfi_correct()
336 		temp_addr[i * 2 + 1] = (readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4)  in ma35_nfi_correct()
355 			value = readl(nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nfi_correct()
357 			writel(value, nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nfi_correct()
375 			offset = (readl(nand->regs + MA35_NFI_REG_NANDRACTL) & 0x1ff) -  in ma35_nfi_correct()
380 			value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain);  in ma35_nfi_correct()
382 			writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain);  in ma35_nfi_correct()
389 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nfi_ecc_check()  local
398 		status = readl(nand->regs + MA35_NFI_REG_NANDECCES0 + j * 4);  in ma35_nfi_ecc_check()
412 				dev_err(nand->dev, "uncorrectable error! 0x%4x\n", status);  in ma35_nfi_ecc_check()
421 static void ma35_nand_dmac_init(struct ma35_nand_info *nand)  in ma35_nand_dmac_init()  argument
424 	writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);  in ma35_nand_dmac_init()
425 	writel(DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);  in ma35_nand_dmac_init()
428 	writel(INT_DMA | INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_dmac_init()
429 	writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN);  in ma35_nand_dmac_init()
434 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_do_write()  local
442 			writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA);  in ma35_nand_do_write()
446 	ma35_nand_dmac_init(nand);  in ma35_nand_do_write()
449 	reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nand_do_write()
451 		writel(reg & 0xffff, nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nand_do_write()
453 	dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_TO_DEVICE);  in ma35_nand_do_write()
454 	ret = dma_mapping_error(nand->dev, dma_addr);  in ma35_nand_do_write()
456 		dev_err(nand->dev, "dma mapping error\n");  in ma35_nand_do_write()
459 	dma_sync_single_for_device(nand->dev, dma_addr, len, DMA_TO_DEVICE);  in ma35_nand_do_write()
461 	reinit_completion(&nand->complete);  in ma35_nand_do_write()
462 	writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);  in ma35_nand_do_write()
463 	writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN,  in ma35_nand_do_write()
464 	       nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_do_write()
465 	ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000));  in ma35_nand_do_write()
467 		dev_err(nand->dev, "write timeout\n");  in ma35_nand_do_write()
471 	dma_unmap_single(nand->dev, dma_addr, len, DMA_TO_DEVICE);  in ma35_nand_do_write()
478 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_do_read()  local
486 			addr[i] = readb(nand->regs + MA35_NFI_REG_NANDDATA);  in ma35_nand_do_read()
490 	ma35_nand_dmac_init(nand);  in ma35_nand_do_read()
493 	dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_FROM_DEVICE);  in ma35_nand_do_read()
494 	ret = dma_mapping_error(nand->dev, dma_addr);  in ma35_nand_do_read()
496 		dev_err(nand->dev, "dma mapping error\n");  in ma35_nand_do_read()
500 	reinit_completion(&nand->complete);  in ma35_nand_do_read()
501 	writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);  in ma35_nand_do_read()
502 	writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN,  in ma35_nand_do_read()
503 	       nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_do_read()
504 	ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000));  in ma35_nand_do_read()
506 		dev_err(nand->dev, "read timeout\n");  in ma35_nand_do_read()
510 	dma_unmap_single(nand->dev, dma_addr, len, DMA_FROM_DEVICE);  in ma35_nand_do_read()
512 	reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_do_read()
516 			writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);  in ma35_nand_do_read()
517 			writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST,  in ma35_nand_do_read()
518 			       nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_do_read()
520 		writel(INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_do_read()
530 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_format_subpage()  local
538 	reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL) | 0xffff0000;  in ma35_nand_format_subpage()
539 	memset(nand->buffer, 0xff, mtd->writesize);  in ma35_nand_format_subpage()
541 		memcpy(nand->buffer + i * chip->ecc.size,  in ma35_nand_format_subpage()
545 	writel(reg, nand->regs + MA35_NFI_REG_NANDRACTL);  in ma35_nand_format_subpage()
554 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_write_subpage_hwecc()  local
560 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_subpage_hwecc()
561 	writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_subpage_hwecc()
571 	ma35_nand_do_write(chip, nand->buffer, mtd->writesize);  in ma35_nand_write_subpage_hwecc()
575 	reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL);  in ma35_nand_write_subpage_hwecc()
585 	writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);  in ma35_nand_write_subpage_hwecc()
587 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_subpage_hwecc()
588 	writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_subpage_hwecc()
596 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_write_page_hwecc()  local
601 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_page_hwecc()
602 	writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_page_hwecc()
619 	writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_write_page_hwecc()
627 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_read_subpage_hwecc()  local
633 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_subpage_hwecc()
634 	writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_subpage_hwecc()
640 	reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nand_read_subpage_hwecc()
650 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_subpage_hwecc()
651 	writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_subpage_hwecc()
659 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_read_page_hwecc()  local
665 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_page_hwecc()
666 	writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_page_hwecc()
672 	reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nand_read_page_hwecc()
682 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_page_hwecc()
683 	writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_read_page_hwecc()
690 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_read_oob_hwecc()  local
700 	reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);  in ma35_nand_read_oob_hwecc()
707 static inline void ma35_hw_init(struct ma35_nand_info *nand)  in ma35_hw_init()  argument
712 	writel(DISABLE_WP, nand->regs + MA35_NFI_REG_NANDECTL);  in ma35_hw_init()
715 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_hw_init()
717 	writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_hw_init()
722 	struct ma35_nand_info *nand = (struct ma35_nand_info *)id;  in ma35_nand_irq()  local
725 	isr = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_irq()
727 		writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTSTS);  in ma35_nand_irq()
728 		complete(&nand->complete);  in ma35_nand_irq()
737 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nand_attach_chip()  local
747 	reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK);  in ma35_nand_attach_chip()
750 		writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_attach_chip()
753 		writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_attach_chip()
756 		writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);  in ma35_nand_attach_chip()
774 		return ma35_nand_hwecc_init(chip, nand);  in ma35_nand_attach_chip()
789 	struct ma35_nand_info *nand = nand_get_controller_data(chip);  in ma35_nfc_exec_instr()  local
796 		writel(instr->ctx.cmd.opcode, nand->regs + MA35_NFI_REG_NANDCMD);  in ma35_nfc_exec_instr()
802 				       nand->regs + MA35_NFI_REG_NANDADDR);  in ma35_nfc_exec_instr()
805 				       nand->regs + MA35_NFI_REG_NANDADDR);  in ma35_nfc_exec_instr()
815 		return readl_poll_timeout(nand->regs + MA35_NFI_REG_NANDINTSTS, status,  in ma35_nfc_exec_instr()
852 static int ma35_nand_chip_init(struct device *dev, struct ma35_nand_info *nand,  in ma35_nand_chip_init()  argument
887 		if (test_and_set_bit(cs, &nand->assigned_cs)) {  in ma35_nand_chip_init()
896 	chip->controller = &nand->controller;  in ma35_nand_chip_init()
899 	nand_set_controller_data(chip, nand);  in ma35_nand_chip_init()
916 	list_add_tail(&nvtnand->node, &nand->chips);  in ma35_nand_chip_init()
921 static void ma35_chips_cleanup(struct ma35_nand_info *nand)  in ma35_chips_cleanup()  argument
927 	list_for_each_entry_safe(nvtnand, tmp, &nand->chips, node) {  in ma35_chips_cleanup()
936 static int ma35_nand_chips_init(struct device *dev, struct ma35_nand_info *nand)  in ma35_nand_chips_init()  argument
942 		ret = ma35_nand_chip_init(dev, nand, nand_np);  in ma35_nand_chips_init()
944 			ma35_chips_cleanup(nand);  in ma35_nand_chips_init()
953 	struct ma35_nand_info *nand;  in ma35_nand_probe()  local
956 	nand = devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL);  in ma35_nand_probe()
957 	if (!nand)  in ma35_nand_probe()
960 	nand_controller_init(&nand->controller);  in ma35_nand_probe()
961 	INIT_LIST_HEAD(&nand->chips);  in ma35_nand_probe()
962 	nand->controller.ops = &ma35_nfc_ops;  in ma35_nand_probe()
964 	init_completion(&nand->complete);  in ma35_nand_probe()
966 	nand->regs = devm_platform_ioremap_resource(pdev, 0);  in ma35_nand_probe()
967 	if (IS_ERR(nand->regs))  in ma35_nand_probe()
968 		return PTR_ERR(nand->regs);  in ma35_nand_probe()
970 	nand->dev = &pdev->dev;  in ma35_nand_probe()
972 	nand->clk = devm_clk_get_enabled(&pdev->dev, "nand_gate");  in ma35_nand_probe()
973 	if (IS_ERR(nand->clk))  in ma35_nand_probe()
974 		return dev_err_probe(&pdev->dev, PTR_ERR(nand->clk),  in ma35_nand_probe()
975 				     "failed to find NAND clock\n");  in ma35_nand_probe()
977 	nand->irq = platform_get_irq(pdev, 0);  in ma35_nand_probe()
978 	if (nand->irq < 0)  in ma35_nand_probe()
979 		return dev_err_probe(&pdev->dev, nand->irq,  in ma35_nand_probe()
982 	ret = devm_request_irq(&pdev->dev, nand->irq, ma35_nand_irq,  in ma35_nand_probe()
983 			       IRQF_TRIGGER_HIGH, "ma35d1-nand-controller", nand);  in ma35_nand_probe()
985 		dev_err(&pdev->dev, "failed to request NAND irq\n");  in ma35_nand_probe()
989 	platform_set_drvdata(pdev, nand);  in ma35_nand_probe()
991 	writel(GRST | NAND_EN, nand->regs + MA35_NFI_REG_GCTL);  in ma35_nand_probe()
992 	ma35_hw_init(nand);  in ma35_nand_probe()
993 	ret = ma35_nand_chips_init(&pdev->dev, nand);  in ma35_nand_probe()
995 		dev_err(&pdev->dev, "failed to init NAND chips\n");  in ma35_nand_probe()
996 		clk_disable(nand->clk);  in ma35_nand_probe()
1005 	struct ma35_nand_info *nand = platform_get_drvdata(pdev);  in ma35_nand_remove()  local
1007 	ma35_chips_cleanup(nand);  in ma35_nand_remove()
1011 	{ .compatible = "nuvoton,ma35d1-nand-controller" },
1018 		.name = "ma35d1-nand-controller",
1027 MODULE_DESCRIPTION("Nuvoton ma35 NAND driver");