24  *				by ECC (value in pages)
26  *				by ECC (value in pages)
67  *				protected by ECC
71  *				of a page, consisting of all data, ecc, spare
74  *				by ECC
75  * @ecc_bytes_hw:		ECC bytes used by controller hardware for this
82  *				ecc/non-ecc mode for the current nand flash
89  * @use_ecc:			request the controller to use ECC for the
91  * @bch_enabled:		flag to tell whether BCH ECC mode is used
147 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)  in qcom_nandc_is_last_cw()  argument
149 	return cw == (ecc->steps - 1);  in qcom_nandc_is_last_cw()
221 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in nandc_set_read_loc()  local
224 	if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))  in nandc_set_read_loc()
229 	if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))  in nandc_set_read_loc()
330 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in config_nand_cw_read()  local
334 	if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))  in config_nand_cw_read()
398  * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
401  * when using RS ECC, the HW reports the same erros when reading an erased CW,
405  * verify if the page is erased or not, and fix up the page for RS ECC by
477 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_cw_raw()  local
489 		raw_cw = ecc->steps - 1;  in qcom_nandc_read_cw_raw()
496 	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_read_cw_raw()
499 	if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) {  in qcom_nandc_read_cw_raw()
500 		data_size2 = ecc->size - data_size1 -  in qcom_nandc_read_cw_raw()
501 			     ((ecc->steps - 1) * 4);  in qcom_nandc_read_cw_raw()
502 		oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +  in qcom_nandc_read_cw_raw()
546  * number of 0 in each CW for which ECC engine returns the uncorrectable
548  * equal to the ecc->strength for each CW.
556  *    The BBM and spare bytes bit flip won’t affect the ECC so don’t check
566 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in check_for_erased_page()  local
578 	for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {  in check_for_erased_page()
579 		if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) {  in check_for_erased_page()
580 			data_size = ecc->size - ((ecc->steps - 1) * 4);  in check_for_erased_page()
581 			oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;  in check_for_erased_page()
589 		cw_oob_buf = oob_buf + (cw * ecc->bytes);  in check_for_erased_page()
603 						  0, ecc->strength);  in check_for_erased_page()
617  * errors. this is equivalent to what 'ecc->correct()' would do.
625 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in parse_read_errors()  local
635 	for (i = 0; i < ecc->steps; i++, buf++) {  in parse_read_errors()
639 		if (qcom_nandc_is_last_cw(ecc, i)) {  in parse_read_errors()
640 			data_len = ecc->size - ((ecc->steps - 1) << 2);  in parse_read_errors()
641 			oob_len = ecc->steps << 2;  in parse_read_errors()
652 		 * Check ECC failure for each codeword. ECC failure can  in parse_read_errors()
654 		 * 1. If number of bitflips are greater than ECC engine  in parse_read_errors()
661 			 * For BCH ECC, ignore erased codeword errors, if  in parse_read_errors()
667 			 * For RS ECC, HW reports the erased CW by placing  in parse_read_errors()
690 		 * No ECC or operational errors happened. Check the number of  in parse_read_errors()
704 			oob_buf += oob_len + ecc->bytes;  in parse_read_errors()
719  * helper to perform the actual page read operation, used by ecc->read_page(),
720  * ecc->read_oob()
727 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in read_page_ecc()  local
734 	for (i = 0; i < ecc->steps; i++) {  in read_page_ecc()
737 		if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {  in read_page_ecc()
738 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in read_page_ecc()
739 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in read_page_ecc()
766 		 * when ecc is enabled, the controller doesn't read the real  in read_page_ecc()
768 		 * consistent layout across RAW and ECC reads, we just  in read_page_ecc()
805 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in copy_last_cw()  local
816 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in copy_last_cw()
817 	update_rw_regs(host, 1, true, ecc->steps - 1);  in copy_last_cw()
819 	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);  in copy_last_cw()
893 /* implements ecc->read_page() */
899 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_page()  local
911 	update_rw_regs(host, ecc->steps, true, 0);  in qcom_nandc_read_page()
921 /* implements ecc->read_page_raw() */
927 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_page_raw()  local
934 	for (cw = 0; cw < ecc->steps; cw++) {  in qcom_nandc_read_page_raw()
941 		oob_buf += ecc->bytes;  in qcom_nandc_read_page_raw()
947 /* implements ecc->read_oob() */
952 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_oob()  local
962 	update_rw_regs(host, ecc->steps, true, 0);  in qcom_nandc_read_oob()
967 /* implements ecc->write_page() */
973 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page()  local
992 	update_rw_regs(host, ecc->steps, false, 0);  in qcom_nandc_write_page()
995 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page()
998 		if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {  in qcom_nandc_write_page()
999 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_page()
1000 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page()
1004 			oob_size = ecc->bytes;  in qcom_nandc_write_page()
1008 				    i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);  in qcom_nandc_write_page()
1011 		 * when ECC is enabled, we don't really need to write anything  in qcom_nandc_write_page()
1013 		 * just contain ECC bytes that's written by the controller  in qcom_nandc_write_page()
1017 		if (qcom_nandc_is_last_cw(ecc, i)) {  in qcom_nandc_write_page()
1039 /* implements ecc->write_page_raw() */
1047 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page_raw()  local
1062 	update_rw_regs(host, ecc->steps, false, 0);  in qcom_nandc_write_page_raw()
1065 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page_raw()
1069 		data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_write_page_raw()
1072 		if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {  in qcom_nandc_write_page_raw()
1073 			data_size2 = ecc->size - data_size1 -  in qcom_nandc_write_page_raw()
1074 				     ((ecc->steps - 1) << 2);  in qcom_nandc_write_page_raw()
1075 			oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page_raw()
1113  * implements ecc->write_oob()
1116  * since ECC is calculated for the combined codeword. So update the OOB from
1124 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_oob()  local
1136 	data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_oob()
1144 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_write_oob()
1166 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_bad()  local
1173 	 * the beginning of the last codeword, we don't care about reading ecc  in qcom_nandc_block_bad()
1189 	bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_block_bad()
1203 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_markbad()  local
1220 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_block_markbad()
1221 	update_rw_regs(host, 1, false, ecc->steps - 1);  in qcom_nandc_block_markbad()
1240  * Layout with ECC enabled:
1244  * |    DATA   xx..ECC..yy|  |    DATA     **SPARE**xx..ECC..yy|
1252  * . = ECC bytes
1262  * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
1263  * the number of ECC bytes vary based on the ECC strength and the bus width.
1266  * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
1269  * When we access a page with ECC enabled, the reserved bytes(s) are not
1274  * Layout with ECC disabled:
1278  * |  DATA1  yy  DATA2   xx..ECC..|  |  DATA1  bb  DATA2   **SPARE**xx..ECC..|
1286  * . = ECC bytes
1293  * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
1297  * In order to have a consistent layout between RAW and ECC modes, we assume
1302  * |yyxx..ECC..|  |bb*FREEOOB*xx..ECC..|
1310  * . = ECC bytes
1312  * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
1314  * b = Real bad block byte(s) (inaccessible when ECC enabled)
1316  * This layout is read as is when ECC is disabled. When ECC is enabled, the
1318  * and assumed as 0xffs when we read a page/oob. The ECC, unused and
1319  * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
1327 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_ecc()  local
1333 		oobregion->length = (ecc->bytes * (ecc->steps - 1)) +  in qcom_nand_ooblayout_ecc()
1349 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_free()  local
1354 	oobregion->length = ecc->steps * 4;  in qcom_nand_ooblayout_free()
1355 	oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;  in qcom_nand_ooblayout_free()
1361 	.ecc = qcom_nand_ooblayout_ecc,
1378 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_attach_chip()  local
1385 	ecc->size = NANDC_STEP_SIZE;  in qcom_nand_attach_chip()
1390 	 * Each CW has 4 available OOB bytes which will be protected with ECC  in qcom_nand_attach_chip()
1391 	 * so remaining bytes can be used for ECC.  in qcom_nand_attach_chip()
1396 		dev_err(nandc->dev, "No valid ECC settings possible\n");  in qcom_nand_attach_chip()
1400 	if (ecc->strength >= 8) {  in qcom_nand_attach_chip()
1401 		/* 8 bit ECC defaults to BCH ECC on all platforms */  in qcom_nand_attach_chip()
1416 		 * if the controller supports BCH for 4 bit ECC, the controller  in qcom_nand_attach_chip()
1417 		 * uses lesser bytes for ECC. If RS is used, the ECC bytes is  in qcom_nand_attach_chip()
1449 	 * we consider ecc->bytes as the sum of all the non-data content in a  in qcom_nand_attach_chip()
1451 	 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit  in qcom_nand_attach_chip()
1452 	 * ECC and 12 bytes for 4 bit ECC  in qcom_nand_attach_chip()
1454 	ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;  in qcom_nand_attach_chip()
1456 	ecc->read_page		= qcom_nandc_read_page;  in qcom_nand_attach_chip()
1457 	ecc->read_page_raw	= qcom_nandc_read_page_raw;  in qcom_nand_attach_chip()
1458 	ecc->read_oob		= qcom_nandc_read_oob;  in qcom_nand_attach_chip()
1459 	ecc->write_page		= qcom_nandc_write_page;  in qcom_nand_attach_chip()
1460 	ecc->write_page_raw	= qcom_nandc_write_page_raw;  in qcom_nand_attach_chip()
1461 	ecc->write_oob		= qcom_nandc_write_oob;  in qcom_nand_attach_chip()
1463 	ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;  in qcom_nand_attach_chip()
1485 	 * spare data with ECC too. We protect spare data by default, so we set  in qcom_nand_attach_chip()
1491 	 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes  in qcom_nand_attach_chip()
1492 	 * for 8 bit ECC  in qcom_nand_attach_chip()
1494 	host->cw_size = host->cw_data + ecc->bytes;  in qcom_nand_attach_chip()
1546 		host->cw_size, host->cw_data, ecc->strength, ecc->bytes,  in qcom_nand_attach_chip()
1693 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_read_status_exec()  local
1707 	num_cw = nandc->exec_opwrite ? ecc->steps : 1;  in qcom_read_status_exec()
2161 	 * of a page with ECC disabled. currently, the nand_base and nand_bbt  in qcom_nand_host_init_and_register()
2162 	 * helpers don't allow us to read BB from a nand chip with ECC  in qcom_nand_host_init_and_register()