15 #define USE_CLSR	BIT(0)
18 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
19 #define SPINOR_OP_CLPEF		0x82	/* Clear program/erase failure flags */
20 #define SPINOR_OP_CYPRESS_DIE_ERASE		0x61	/* Chip (die) erase */
21 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
22 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
23 #define SPINOR_REG_CYPRESS_VREG			0x00800000
24 #define SPINOR_REG_CYPRESS_STR1			0x0
27 #define SPINOR_REG_CYPRESS_CFR1			0x2
29 #define SPINOR_REG_CYPRESS_CFR2			0x3
32 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK	GENMASK(3, 0)
33 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24	0xb
35 #define SPINOR_REG_CYPRESS_CFR3			0x4
37 #define SPINOR_REG_CYPRESS_CFR5			0x6
40 #define SPINOR_REG_CYPRESS_CFR5_OPI		BIT(0)
45 #define SPINOR_OP_CYPRESS_RD_FAST		0xee
46 #define SPINOR_REG_CYPRESS_ARCFN		0x00000006
50 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0),		\
51 		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
53 		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
56 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0),		\
57 		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
58 		   SPI_MEM_OP_DUMMY(ndummy, 0),				\
59 		   SPI_MEM_OP_DATA_IN(1, buf, 0))
62 	SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),				\
93 						       NULL, 0);  in spansion_nor_clear_sr()
105 					  0, nor->bouncebuf);  in cypress_nor_sr_ready_and_clear_reg()
118 	if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {  in cypress_nor_sr_ready_and_clear_reg()
119 		if (nor->bouncebuf[0] & SR_E_ERR)  in cypress_nor_sr_ready_and_clear_reg()
133 	return !(nor->bouncebuf[0] & SR_WIP);  in cypress_nor_sr_ready_and_clear_reg()
141  * Return: 1 if ready, 0 if not ready, -errno on errors.
150 	for (i = 0; i < params->n_dice; i++) {  in cypress_nor_sr_ready_and_clear()
153 		if (ret < 0)  in cypress_nor_sr_ready_and_clear()
155 		else if (ret == 0)  in cypress_nor_sr_ready_and_clear()
156 			return 0;  in cypress_nor_sr_ready_and_clear()
170 		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf);  in cypress_nor_set_memlat()
189 	return 0;  in cypress_nor_set_memlat()
198 	buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;  in cypress_nor_set_octal_dtr_bits()
213 	for (i = 0; i < params->n_dice; i++) {  in cypress_nor_octal_dtr_en()
236 	return 0;  in cypress_nor_octal_dtr_en()
247 	 * just initialize the value to 0 and let the transaction go on.  in cypress_nor_set_single_spi_bits()
249 	buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS;  in cypress_nor_set_single_spi_bits()
250 	buf[1] = 0;  in cypress_nor_set_single_spi_bits()
263 	for (i = 0; i < params->n_dice; i++) {  in cypress_nor_octal_dtr_dis()
271 	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);  in cypress_nor_octal_dtr_dis()
280 	return 0;  in cypress_nor_octal_dtr_dis()
291 		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0,  in cypress_nor_quad_enable_volatile_reg()
298 	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN)  in cypress_nor_quad_enable_volatile_reg()
299 		return 0;  in cypress_nor_quad_enable_volatile_reg()
302 	nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN;  in cypress_nor_quad_enable_volatile_reg()
310 	cfr1v_written = nor->bouncebuf[0];  in cypress_nor_quad_enable_volatile_reg()
314 		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0,  in cypress_nor_quad_enable_volatile_reg()
320 	if (nor->bouncebuf[0] != cfr1v_written) {  in cypress_nor_quad_enable_volatile_reg()
325 	return 0;  in cypress_nor_quad_enable_volatile_reg()
340  * Return: 0 on success, -errno otherwise.
349 	for (i = 0; i < params->n_dice; i++) {  in cypress_nor_quad_enable_volatile()
356 	return 0;  in cypress_nor_quad_enable_volatile()
370  * Return: 0 on success, -errno otherwise.
376 		CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0,  in cypress_nor_determine_addr_mode_by_sr1()
389 	is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);  in cypress_nor_determine_addr_mode_by_sr1()
392 		CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,  in cypress_nor_determine_addr_mode_by_sr1()
398 	is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);  in cypress_nor_determine_addr_mode_by_sr1()
407 	return 0;  in cypress_nor_determine_addr_mode_by_sr1()
419  * Return: 0 on success, -errno otherwise.
451 					  0, nor->bouncebuf);  in cypress_nor_set_addr_mode_nbytes()
456 	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) {  in cypress_nor_set_addr_mode_nbytes()
467 	return 0;  in cypress_nor_set_addr_mode_nbytes()
478  * Return: 0 on success, -errno otherwise.
484 					  0, 0, nor->bouncebuf);  in cypress_nor_get_page_size()
494 	for (i = 0; i < params->n_dice; i++) {  in cypress_nor_get_page_size()
501 		if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ))  in cypress_nor_get_page_size()
502 			return 0;  in cypress_nor_get_page_size()
507 	return 0;  in cypress_nor_get_page_size()
542 	/* ARCFN value must be 0 if uniform sector is selected  */  in s25fs256t_post_bfpt_fixup()
543 	if (nor->bouncebuf[0])  in s25fs256t_post_bfpt_fixup()
546 	return 0;  in s25fs256t_post_bfpt_fixup()
562 	params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG;  in s25fs256t_post_sfdp_fixup()
578 	return 0;  in s25fs256t_late_init()
601 	return 0;  in s25hx_t_post_bfpt_fixup()
624 	for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {  in s25hx_t_post_sfdp_fixup()
650 	return 0;  in s25hx_t_late_init()
667  * Return: 0 on success, -errno otherwise.
691 	 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.  in s28hx_t_post_sfdp_fixup()
693 	if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)  in s28hx_t_post_sfdp_fixup()
709 	 * address bytes needed for Read Status Register command as 0 but the  in s28hx_t_post_sfdp_fixup()
732 	return 0;  in s28hx_t_late_init()
754 	return 0;  in s25fs_s_nor_post_bfpt_fixups()
763 		.id = SNOR_ID(0x01, 0x02, 0x12),
767 		.id = SNOR_ID(0x01, 0x02, 0x13),
771 		.id = SNOR_ID(0x01, 0x02, 0x14),
775 		.id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00),
780 		.id = SNOR_ID(0x01, 0x02, 0x15),
784 		.id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00),
789 		.id = SNOR_ID(0x01, 0x02, 0x16),
793 		.id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80),
800 		.id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81),
807 		.id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80),
813 		.id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x81),
819 		.id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80),
827 		.id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81),
835 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
840 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01),
844 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80),
851 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00),
858 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80),
864 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81),
871 		.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
877 		.id = SNOR_ID(0x01, 0x40, 0x13),
882 		.id = SNOR_ID(0x01, 0x40, 0x14),
887 		.id = SNOR_ID(0x01, 0x40, 0x15),
892 		.id = SNOR_ID(0x01, 0x40, 0x16),
897 		.id = SNOR_ID(0x01, 0x40, 0x17),
902 		.id = SNOR_ID(0x01, 0x60, 0x17),
908 		.id = SNOR_ID(0x01, 0x60, 0x18),
914 		.id = SNOR_ID(0x01, 0x60, 0x19),
920 		.id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f),
926 		.id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
931 		.id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
936 		.id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
941 		.id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
946 		.id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
951 		.id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
956 		.id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
962 		.id = SNOR_ID(0x34, 0x5a, 0x19),
966 		.id = SNOR_ID(0x34, 0x5a, 0x1a),
971 		.id = SNOR_ID(0x34, 0x5a, 0x1b),
977 		.id = SNOR_ID(0x34, 0x5a, 0x1c),
981 		.id = SNOR_ID(0x34, 0x5b, 0x19),
985 		.id = SNOR_ID(0x34, 0x5b, 0x1a),
990 		.id = SNOR_ID(0x34, 0x5b, 0x1b),
995 		.id = SNOR_ID(0x34, 0x5b, 0x1c),
1000 		.id = SNOR_ID(0xef, 0x40, 0x13),
1005 		.id = SNOR_ID(0xef, 0x40, 0x14),
1010 		.id = SNOR_ID(0xef, 0x40, 0x15),
1015 		.id = SNOR_ID(0xef, 0x40, 0x17),
1027  * Return: 1 if ready, 0 if not ready, -errno on errors.
1037 	if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {  in spansion_nor_sr_ready_and_clear()
1038 		if (nor->bouncebuf[0] & SR_E_ERR)  in spansion_nor_sr_ready_and_clear()
1058 	return !(nor->bouncebuf[0] & SR_WIP);  in spansion_nor_sr_ready_and_clear()
1090 	return 0;  in spansion_nor_late_init()