Lines Matching +full:0 +full:- +full:2
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
6 * Copyright (C) 2019-2021 Linutronix GmbH
19 #include <linux/platform_data/hirschmann-hellcreek.h>
29 * - 0: CPU
30 * - 1: Tunnel
31 * - 2: TSN front port 1
32 * - 3: TSN front port 2
33 * - ...
35 #define CPU_PORT 0
38 #define HELLCREEK_VLAN_NO_MEMBER 0x0
39 #define HELLCREEK_VLAN_UNTAGGED_MEMBER 0x1
40 #define HELLCREEK_VLAN_TAGGED_MEMBER 0x3
45 #define HR_MODID_C (0 * 2)
46 #define HR_REL_L_C (1 * 2)
47 #define HR_REL_H_C (2 * 2)
48 #define HR_BLD_L_C (3 * 2)
49 #define HR_BLD_H_C (4 * 2)
50 #define HR_CTRL_C (5 * 2)
53 #define HR_CTRL_C_ENABLE BIT(0)
55 #define HR_PSEL (0xa6 * 2)
58 #define HR_PSEL_PRTCWSEL_SHIFT 0
59 #define HR_PSEL_PRTCWSEL_MASK GENMASK(2, 0)
61 #define HR_PTCFG (0xa7 * 2)
70 #define HR_PTCFG_BLOCKED BIT(2)
72 #define HR_PTCFG_ADMIN_EN BIT(0)
74 #define HR_PRTCCFG (0xa8 * 2)
75 #define HR_PRTCCFG_PCP_TC_MAP_SHIFT 0
76 #define HR_PRTCCFG_PCP_TC_MAP_MASK GENMASK(2, 0)
78 #define HR_PTPRTCCFG (0xa9 * 2)
81 #define HR_PTPRTCCFG_MAXSDU_SHIFT 0
82 #define HR_PTPRTCCFG_MAXSDU_MASK GENMASK(10, 0)
84 #define HR_CSEL (0x8d * 2)
85 #define HR_CSEL_SHIFT 0
86 #define HR_CSEL_MASK GENMASK(7, 0)
87 #define HR_CRDL (0x8e * 2)
88 #define HR_CRDH (0x8f * 2)
90 #define HR_SWTRC_CFG (0x90 * 2)
91 #define HR_SWTRC0 (0x91 * 2)
92 #define HR_SWTRC1 (0x92 * 2)
93 #define HR_PFREE (0x93 * 2)
94 #define HR_MFREE (0x94 * 2)
96 #define HR_FDBAGE (0x97 * 2)
97 #define HR_FDBMAX (0x98 * 2)
98 #define HR_FDBRDL (0x99 * 2)
99 #define HR_FDBRDM (0x9a * 2)
100 #define HR_FDBRDH (0x9b * 2)
102 #define HR_FDBMDRD (0x9c * 2)
103 #define HR_FDBMDRD_PORTMASK_SHIFT 0
104 #define HR_FDBMDRD_PORTMASK_MASK GENMASK(3, 0)
114 #define HR_FDBWDL (0x9d * 2)
115 #define HR_FDBWDM (0x9e * 2)
116 #define HR_FDBWDH (0x9f * 2)
117 #define HR_FDBWRM0 (0xa0 * 2)
118 #define HR_FDBWRM0_PORTMASK_SHIFT 0
119 #define HR_FDBWRM0_PORTMASK_MASK GENMASK(3, 0)
125 #define HR_FDBWRM1 (0xa1 * 2)
127 #define HR_FDBWRCMD (0xa2 * 2)
130 #define HR_SWCFG (0xa3 * 2)
134 #define HR_SWCFG_LAS_OFF (0x00)
135 #define HR_SWCFG_LAS_ON (0x01)
136 #define HR_SWCFG_LAS_STATIC (0x10)
143 #define HR_SWSTAT (0xa4 * 2)
145 #define HR_SWSTAT_BUSY BIT(0)
147 #define HR_SWCMD (0xa5 * 2)
148 #define HW_SWCMD_FLUSH BIT(0)
150 #define HR_VIDCFG (0xaa * 2)
151 #define HR_VIDCFG_VID_SHIFT 0
152 #define HR_VIDCFG_VID_MASK GENMASK(11, 0)
155 #define HR_VIDMBRCFG (0xab * 2)
156 #define HR_VIDMBRCFG_P0MBR_SHIFT 0
157 #define HR_VIDMBRCFG_P0MBR_MASK GENMASK(1, 0)
158 #define HR_VIDMBRCFG_P1MBR_SHIFT 2
159 #define HR_VIDMBRCFG_P1MBR_MASK GENMASK(3, 2)
165 #define HR_FEABITS0 (0xac * 2)
173 #define TR_QTRACK (0xb1 * 2)
174 #define TR_TGDVER (0xb3 * 2)
175 #define TR_TGDVER_REV_MIN_MASK GENMASK(7, 0)
176 #define TR_TGDVER_REV_MIN_SHIFT 0
179 #define TR_TGDSEL (0xb4 * 2)
180 #define TR_TGDSEL_TDGSEL_MASK GENMASK(1, 0)
181 #define TR_TGDSEL_TDGSEL_SHIFT 0
182 #define TR_TGDCTRL (0xb5 * 2)
183 #define TR_TGDCTRL_GATE_EN BIT(0)
188 #define TR_TGDSTAT0 (0xb6 * 2)
189 #define TR_TGDSTAT1 (0xb7 * 2)
190 #define TR_ESTWRL (0xb8 * 2)
191 #define TR_ESTWRH (0xb9 * 2)
192 #define TR_ESTCMD (0xba * 2)
193 #define TR_ESTCMD_ESTSEC_MASK GENMASK(2, 0)
194 #define TR_ESTCMD_ESTSEC_SHIFT 0
197 #define TR_EETWRL (0xbb * 2)
198 #define TR_EETWRH (0xbc * 2)
199 #define TR_EETCMD (0xbd * 2)
200 #define TR_EETCMD_EETSEC_MASK GEMASK(2, 0)
201 #define TR_EETCMD_EETSEC_SHIFT 0
203 #define TR_CTWRL (0xbe * 2)
204 #define TR_CTWRH (0xbf * 2)
205 #define TR_LCNSL (0xc1 * 2)
206 #define TR_LCNSH (0xc2 * 2)
207 #define TR_LCS (0xc3 * 2)
208 #define TR_GCLDAT (0xc4 * 2)
209 #define TR_GCLDAT_GCLWRGATES_MASK GENMASK(7, 0)
210 #define TR_GCLDAT_GCLWRGATES_SHIFT 0
213 #define TR_GCLTIL (0xc5 * 2)
214 #define TR_GCLTIH (0xc6 * 2)
215 #define TR_GCLCMD (0xc7 * 2)
216 #define TR_GCLCMD_GCLWRADR_MASK GENMASK(7, 0)
217 #define TR_GCLCMD_GCLWRADR_SHIFT 0
257 /* Per-port timestamping resources */
260 /* Per-port Qbv schedule information */
305 * cannot be armed directly to $base_time - 8 + X, because for large deltas the
308 #define HELLCREEK_SCHEDULE_PERIOD (2 * HZ)