Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
23 #define OVER_TEMP_INT BIT(28)
24 #define HSR_INT BIT(27)
25 #define PIO_INT BIT(26)
26 #define POR_READY_INT BIT(25)
35 /* 1 - Global */
37 #define SW_CLK125_ENB BIT(1)
38 #define SW_CLK25_ENB BIT(0)
41 #define SW_CASCADE_ID_CFG BIT(15)
42 #define SW_VPHY_ADD_CFG BIT(0)
44 /* 2 - PHY Control */
46 #define SW_VPHY_DISABLE BIT(31)
48 /* 3 - Operation Control */
51 #define SW_DOUBLE_TAG BIT(7)
52 #define SW_OVER_TEMP_ENABLE BIT(2)
53 #define SW_RESET BIT(1)
57 #define SW_VLAN_ENABLE BIT(7)
58 #define SW_DROP_INVALID_VID BIT(6)
60 #define SW_RESV_MCAST_ENABLE BIT(2)
64 #define UNICAST_LEARN_DISABLE BIT(7)
65 #define SW_FLUSH_STP_TABLE BIT(5)
66 #define SW_FLUSH_MSTP_TABLE BIT(4)
67 #define SW_SRC_ADDR_FILTER BIT(3)
68 #define SW_AGING_ENABLE BIT(2)
69 #define SW_FAST_AGING BIT(1)
70 #define SW_LINK_AUTO_AGING BIT(0)
74 #define SW_AGE_CNT_IN_MICROSEC BIT(7)
83 #define SW_NEW_BACKOFF BIT(7)
84 #define SW_PAUSE_UNH_MODE BIT(1)
85 #define SW_AGGR_BACKOFF BIT(0)
88 #define SW_SHORT_IFG BIT(7)
89 #define MULTICAST_STORM_DISABLE BIT(6)
90 #define SW_BACK_PRESSURE BIT(5)
91 #define FAIR_FLOW_CTRL BIT(4)
92 #define NO_EXC_COLLISION_DROP BIT(3)
93 #define SW_LEGAL_PACKET_DISABLE BIT(1)
94 #define SW_PASS_SHORT_FRAME BIT(0)
97 #define SW_MIB_COUNTER_FLUSH BIT(7)
98 #define SW_MIB_COUNTER_FREEZE BIT(6)
100 /* 4 - LUE */
104 #define ALU_V_OVERRIDE BIT(31)
105 #define ALU_V_USE_FID BIT(30)
108 /* 7 - VPhy */
114 #define VPHY_IND_WRITE BIT(1)
115 #define VPHY_IND_BUSY BIT(0)
118 #define VPHY_SMI_INDIRECT_ENABLE BIT(15)
119 #define VPHY_SW_LOOPBACK BIT(14)
120 #define VPHY_MDIO_INTERNAL_ENABLE BIT(13)
121 #define VPHY_SPI_INDIRECT_ENABLE BIT(12)
126 #define VPHY_MODE_SGMII 2
128 #define VPHY_SW_COLLISION_TEST BIT(7)
130 #define VPHY_SPEED_DUPLEX_STAT_S 2
131 #define VPHY_SPEED_1000 BIT(4)
132 #define VPHY_SPEED_100 BIT(3)
133 #define VPHY_FULL_DUPLEX BIT(2)
137 /* 0 - Operation */
141 #define PORT_TAS_INT BIT(5)
142 #define PORT_QCI_INT BIT(4)
143 #define PORT_SGMII_INT BIT(3)
144 #define PORT_PTP_INT BIT(2)
145 #define PORT_PHY_INT BIT(1)
146 #define PORT_ACL_INT BIT(0)
152 #define PORT_MAC_LOOPBACK BIT(7)
153 #define PORT_MAC_REMOTE_LOOPBACK BIT(6)
154 #define PORT_K2L_INSERT_ENABLE BIT(5)
155 #define PORT_K2L_DEBUG_ENABLE BIT(4)
156 #define PORT_TAIL_TAG_ENABLE BIT(2)
159 /* 1 - Phy */
163 /* 3 - xMII */
164 #define PORT_SGMII_SEL BIT(7)
165 #define PORT_GRXC_ENABLE BIT(0)
167 #define PORT_MII_SEL_EDGE BIT(5)
172 #define PORT_DLL_RESET BIT(15)
175 /* 4 - MAC */
177 #define PORT_CHECK_LENGTH BIT(2)
178 #define PORT_BROADCAST_STORM BIT(1)
179 #define PORT_JUMBO_PACKET BIT(0)
182 #define PORT_BACK_PRESSURE BIT(3)
183 #define PORT_PASS_ALL BIT(0)
188 /* 8 - Classification and Policing */
190 #define PORT_HIGHEST_PRIO BIT(7)
191 #define PORT_OR_PRIO BIT(6)
192 #define PORT_MAC_PRIO_ENABLE BIT(4)
193 #define PORT_VLAN_PRIO_ENABLE BIT(3)
194 #define PORT_802_1P_PRIO_ENABLE BIT(2)
195 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
196 #define PORT_ACL_PRIO_ENABLE BIT(0)
200 /* 9 - Shaping */
207 #define LAN937X_RGMII_2_PORT (RGMII_2_PORT_NUM - 1)
208 #define LAN937X_RGMII_1_PORT (RGMII_1_PORT_NUM - 1)
210 #define RGMII_1_TX_DELAY_2NS 2
215 #define LAN937X_TAG_LEN 2