36 			       u32 reg, u32 mask, u32 val)  in owl_emac_reg_update()
99 	u32 val = owl_emac_irq_status(priv);  in owl_emac_irq_clear()  local
315 static u32 owl_emac_dma_cmd_set_tx(struct owl_emac_priv *priv, u32 status)  in owl_emac_dma_cmd_set_tx()
326 static u32 owl_emac_dma_cmd_set(struct owl_emac_priv *priv, u32 status)  in owl_emac_dma_cmd_set()
358 	u32 val, status;  in owl_emac_update_link_state()  local
497 	u32 status, control;  in owl_emac_setup_frame_xmit()  local
573 	u32 status, control;  in owl_emac_ndo_start_xmit()  local
638 	u32 status;  in owl_emac_tx_complete_tail()  local
700 	u32 status;  in owl_emac_tx_complete()  local
755 	u32 status;  in owl_emac_rx_process()  local
870 	u32 status, proc_status;  in owl_emac_poll()  local
942 	u32 val;  in owl_emac_mdio_clock_enable()  local
967 	u32 val;  in owl_emac_core_sw_reset()  local
1131 	u32 status, val = 0;  in owl_emac_ndo_set_rx_mode()  local
1245 static void owl_emac_ethtool_set_msglevel(struct net_device *ndev, u32 val)  in owl_emac_ethtool_set_msglevel()
1263 	u32 val;  in owl_emac_mdio_wait()  local
1300 owl_emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)  in owl_emac_mdio_write()