Lines Matching +full:mdi +full:- +full:x
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
528 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
717 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
718 /* Manual MDI configuration */
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
729 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
760 * 15-5: page
761 * 4-0: register offset
784 /* Page 193 - Port Control Registers */
790 /* Page 194 - KMRN Registers */
794 /* MDI Control */