Lines Matching defs:igc_ring
141 struct igc_ring { struct
142 struct igc_q_vector *q_vector; /* backlink to q_vector */
143 struct net_device *netdev; /* back pointer to net_device */
144 struct device *dev; /* device for dma mapping */
145 union { /* array of buffer info structs */
149 void *desc; /* descriptor ring memory */
150 unsigned long flags; /* ring specific flags */
151 void __iomem *tail; /* pointer to ring tail register */
152 dma_addr_t dma; /* phys address of the ring */
153 unsigned int size; /* length of desc. ring in bytes */
155 u16 count; /* number of desc. in the ring */
156 u8 queue_index; /* logical index of the ring*/
157 u8 reg_idx; /* physical index of the ring */
158 bool launchtime_enable; /* true if LaunchTime is enabled */
159 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
160 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
162 u32 start_time;
163 u32 end_time;
164 u32 max_sdu;
165 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
166 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
169 bool cbs_enable; /* indicates if CBS is enabled */
170 s32 idleslope; /* idleSlope in kbps */
171 s32 sendslope; /* sendSlope in kbps */
172 s32 hicredit; /* hiCredit in bytes */
173 s32 locredit; /* loCredit in bytes */
176 u16 next_to_clean;
177 u16 next_to_use;
178 u16 next_to_alloc;
180 union {
216 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; argument