Lines Matching full:hw
13 static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
14 static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
15 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
16 static int ixgbe_ready_eeprom(struct ixgbe_hw *hw);
17 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
18 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
20 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
21 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
22 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
23 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
25 static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
26 static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
27 static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
31 static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
33 static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
43 * @hw: pointer to hardware structure
49 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
55 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
58 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
65 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
75 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) in ixgbe_device_supports_autoneg_fc()
82 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
105 hw_dbg(hw, "Device %x does not support flow control autoneg\n", in ixgbe_device_supports_autoneg_fc()
106 hw->device_id); in ixgbe_device_supports_autoneg_fc()
113 * @hw: pointer to hardware structure
117 int ixgbe_setup_fc_generic(struct ixgbe_hw *hw) in ixgbe_setup_fc_generic() argument
128 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc_generic()
129 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); in ixgbe_setup_fc_generic()
137 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc_generic()
138 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc_generic()
142 * HW will be able to do fc autoneg once the cable is plugged in. If in ixgbe_setup_fc_generic()
145 switch (hw->phy.media_type) { in ixgbe_setup_fc_generic()
148 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc_generic()
154 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
158 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
175 switch (hw->fc.requested_mode) { in ixgbe_setup_fc_generic()
179 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
182 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
192 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
195 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc_generic()
213 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
216 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
220 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc_generic()
224 if (hw->mac.type != ixgbe_mac_X540) { in ixgbe_setup_fc_generic()
229 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
230 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc_generic()
233 if (hw->fc.strict_ieee) in ixgbe_setup_fc_generic()
236 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
237 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
245 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
250 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc_generic()
254 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc_generic()
255 ixgbe_device_supports_autoneg_fc(hw)) { in ixgbe_setup_fc_generic()
256 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
260 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
266 * @hw: pointer to hardware structure
273 int ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
280 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
283 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
286 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
289 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
292 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
294 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
295 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
298 if (hw->mac.ops.setup_fc) { in ixgbe_start_hw_generic()
299 ret_val = hw->mac.ops.setup_fc(hw); in ixgbe_start_hw_generic()
305 switch (hw->mac.type) { in ixgbe_start_hw_generic()
309 hw->mac.ops.get_device_caps(hw, &device_caps); in ixgbe_start_hw_generic()
311 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
313 hw->need_crosstalk_fix = true; in ixgbe_start_hw_generic()
316 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
321 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
328 * @hw: pointer to hw structure
336 int ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
341 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
342 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
343 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
345 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
352 * @hw: pointer to hardware structure
360 int ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
365 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
368 /* Start the HW */ in ixgbe_init_hw_generic()
369 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
373 if (hw->mac.ops.init_led_link_act) in ixgbe_init_hw_generic()
374 hw->mac.ops.init_led_link_act(hw); in ixgbe_init_hw_generic()
381 * @hw: pointer to hardware structure
386 int ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
390 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
391 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
392 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
393 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
395 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
397 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
398 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
399 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
400 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
401 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
402 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
403 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
404 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
406 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
407 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
411 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
412 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
413 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
414 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
415 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
417 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
418 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
421 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
423 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
434 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
435 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
436 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
437 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
438 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
440 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
456 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
457 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
458 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
459 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
461 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
463 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
464 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
465 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
466 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
467 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
468 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
470 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
471 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
475 if (hw->mac.type == ixgbe_mac_X550 || in ixgbe_clear_hw_cntrs_generic()
476 hw->mac.type == ixgbe_mac_X540 || in ixgbe_clear_hw_cntrs_generic()
477 hw->mac.type == ixgbe_mac_e610) { in ixgbe_clear_hw_cntrs_generic()
478 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
479 hw->phy.ops.identify(hw); in ixgbe_clear_hw_cntrs_generic()
482 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
483 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
484 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
485 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
486 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
494 * @hw: pointer to hardware structure
500 int ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
510 hw_dbg(hw, "PBA string buffer was null\n"); in ixgbe_read_pba_string_generic()
514 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
516 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
520 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
522 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
532 hw_dbg(hw, "NVM PBA number is not stored as string\n"); in ixgbe_read_pba_string_generic()
536 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
566 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
568 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
573 hw_dbg(hw, "NVM PBA number section invalid length\n"); in ixgbe_read_pba_string_generic()
579 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
588 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
590 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
603 * @hw: pointer to hardware structure
610 int ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
616 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
617 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
660 * @hw: pointer to hardware structure
664 int ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
668 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_get_bus_info_generic()
671 if (hw->mac.type == ixgbe_mac_e610) in ixgbe_get_bus_info_generic()
672 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS_E610); in ixgbe_get_bus_info_generic()
674 link_status = ixgbe_read_pci_cfg_word(hw, in ixgbe_get_bus_info_generic()
677 hw->bus.width = ixgbe_convert_bus_width(link_status); in ixgbe_get_bus_info_generic()
678 hw->bus.speed = ixgbe_convert_bus_speed(link_status); in ixgbe_get_bus_info_generic()
680 hw->mac.ops.set_lan_id(hw); in ixgbe_get_bus_info_generic()
687 * @hw: pointer to the HW structure
692 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
694 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
698 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
703 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_set_lan_id_multi_port_pcie()
708 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { in ixgbe_set_lan_id_multi_port_pcie()
709 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); in ixgbe_set_lan_id_multi_port_pcie()
717 * @hw: pointer to hardware structure
724 int ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
733 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
736 hw->mac.ops.disable_rx(hw); in ixgbe_stop_adapter_generic()
739 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
742 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
745 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
746 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
749 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
750 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
753 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
757 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
764 return ixgbe_disable_pcie_primary(hw); in ixgbe_stop_adapter_generic()
769 * @hw: pointer to hardware structure
774 int ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) in ixgbe_init_led_link_act_generic() argument
776 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_led_link_act_generic()
780 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_init_led_link_act_generic()
796 switch (hw->mac.type) { in ixgbe_init_led_link_act_generic()
812 * @hw: pointer to hardware structure
815 int ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
817 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
825 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
826 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
833 * @hw: pointer to hardware structure
836 int ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
838 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
846 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
847 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
854 * @hw: pointer to hardware structure
859 int ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
861 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
877 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_init_eeprom_params_generic()
894 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", in ixgbe_init_eeprom_params_generic()
903 * @hw: pointer to hardware structure
910 int ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
916 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
918 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_write_eeprom_buffer_bit_bang_generic()
925 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
927 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
937 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
949 * @hw: pointer to hardware structure
957 static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
967 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
971 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_write_eeprom_buffer_bit_bang()
972 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
977 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
980 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
984 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
989 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
994 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
996 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
997 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
999 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
1005 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
1016 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1020 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1027 * @hw: pointer to hardware structure
1034 int ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
1036 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1038 if (offset >= hw->eeprom.word_size) in ixgbe_write_eeprom_generic()
1041 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
1046 * @hw: pointer to hardware structure
1053 int ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
1059 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1061 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_read_eeprom_buffer_bit_bang_generic()
1073 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1085 * @hw: pointer to hardware structure
1092 static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1101 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1105 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_read_eeprom_buffer_bit_bang()
1106 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1111 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1115 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1120 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1122 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1123 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1126 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1131 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1138 * @hw: pointer to hardware structure
1144 int ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1147 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1149 if (offset >= hw->eeprom.word_size) in ixgbe_read_eeprom_bit_bang_generic()
1152 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1157 * @hw: pointer to hardware structure
1164 int ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1171 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1173 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_read_eerd_buffer_generic()
1180 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1181 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1184 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1187 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eerd_buffer_generic()
1197 * @hw: pointer to hardware structure
1204 static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1214 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1215 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1217 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1221 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1229 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1231 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", in ixgbe_detect_eeprom_page_size_generic()
1232 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1238 * @hw: pointer to hardware structure
1244 int ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1246 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1251 * @hw: pointer to hardware structure
1258 int ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1265 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1267 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_write_eewr_buffer_generic()
1275 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1277 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1281 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1283 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1285 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1295 * @hw: pointer to hardware structure
1301 int ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1303 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1308 * @hw: pointer to hardware structure
1314 static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1321 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1323 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1335 * @hw: pointer to hardware structure
1340 static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1345 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) in ixgbe_acquire_eeprom()
1348 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1352 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1355 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1364 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1365 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
1367 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1374 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1375 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1382 * @hw: pointer to hardware structure
1386 static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1398 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1405 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1411 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1418 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1420 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); in ixgbe_get_eeprom_semaphore()
1427 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1431 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_get_eeprom_semaphore()
1436 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1447 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1448 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1457 * @hw: pointer to hardware structure
1461 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1465 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_release_eeprom_semaphore()
1469 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_release_eeprom_semaphore()
1470 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1475 * @hw: pointer to hardware structure
1477 static int ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1489 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1491 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
1496 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
1504 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
1513 * @hw: pointer to hardware structure
1515 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
1519 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_standby_eeprom()
1523 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1524 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1527 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1528 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1534 * @hw: pointer to hardware structure
1538 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
1545 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_out_eeprom_bits()
1566 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1567 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1571 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1572 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1583 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1584 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1589 * @hw: pointer to hardware structure
1592 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
1605 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1611 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1613 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1619 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1627 * @hw: pointer to hardware structure
1630 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
1637 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_raise_eeprom_clk()
1638 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
1644 * @hw: pointer to hardware structure
1647 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
1654 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_lower_eeprom_clk()
1655 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
1661 * @hw: pointer to hardware structure
1663 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
1667 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_release_eeprom()
1672 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1673 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
1679 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1681 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
1687 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_release_eeprom()
1688 hw->eeprom.semaphore_delay * 2000); in ixgbe_release_eeprom()
1693 * @hw: pointer to hardware structure
1695 int ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
1706 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1707 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1715 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
1716 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1724 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
1725 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1733 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1734 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1748 * @hw: pointer to hardware structure
1754 int ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
1766 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
1768 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1772 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
1778 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
1780 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1799 * @hw: pointer to hardware structure
1801 int ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
1811 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
1813 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_update_eeprom_checksum_generic()
1817 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
1823 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
1830 * @hw: pointer to hardware structure
1838 int ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
1842 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
1846 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_set_rar_generic()
1851 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
1854 * HW expects these in little endian so we reverse the byte in ixgbe_set_rar_generic()
1866 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
1877 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
1878 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_rar_generic()
1879 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
1886 * @hw: pointer to hardware structure
1891 int ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
1894 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
1898 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_clear_rar_generic()
1907 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
1914 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
1915 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_rar_generic()
1916 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
1919 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
1926 * @hw: pointer to hardware structure
1932 int ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
1935 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
1942 if (!is_valid_ether_addr(hw->mac.addr)) { in ixgbe_init_rx_addrs_generic()
1944 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1946 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1949 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); in ixgbe_init_rx_addrs_generic()
1950 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1952 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
1956 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
1958 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
1960 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
1963 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
1965 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
1966 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
1970 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
1971 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
1973 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_init_rx_addrs_generic()
1974 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
1975 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
1977 if (hw->mac.ops.init_uta_tables) in ixgbe_init_rx_addrs_generic()
1978 hw->mac.ops.init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
1985 * @hw: pointer to hardware structure
1995 static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
1999 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
2013 hw_dbg(hw, "MC filter type param set incorrectly\n"); in ixgbe_mta_vector()
2024 * @hw: pointer to hardware structure
2029 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
2035 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
2037 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
2038 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
2051 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); in ixgbe_set_mta()
2056 * @hw: pointer to hardware structure
2064 int ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, in ixgbe_update_mc_addr_list_generic() argument
2074 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); in ixgbe_update_mc_addr_list_generic()
2075 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2078 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_update_mc_addr_list_generic()
2079 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2083 hw_dbg(hw, " Adding the multicast addresses:\n"); in ixgbe_update_mc_addr_list_generic()
2084 ixgbe_set_mta(hw, ha->addr); in ixgbe_update_mc_addr_list_generic()
2088 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2089 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2090 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2092 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2093 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2094 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2096 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); in ixgbe_update_mc_addr_list_generic()
2102 * @hw: pointer to hardware structure
2106 int ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2108 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2111 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2112 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2119 * @hw: pointer to hardware structure
2123 int ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2125 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2128 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2135 * @hw: pointer to hardware structure
2139 int ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2147 if (!hw->fc.pause_time) in ixgbe_fc_enable_generic()
2152 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2153 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2154 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2155 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2156 hw_dbg(hw, "Invalid water mark configuration\n"); in ixgbe_fc_enable_generic()
2163 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
2166 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2169 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2182 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2186 * The code below will actually disable it in the HW. in ixgbe_fc_enable_generic()
2213 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2219 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2220 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2224 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2225 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2226 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2227 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2228 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2230 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2238 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2241 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2245 reg = hw->fc.pause_time * 0x00010001U; in ixgbe_fc_enable_generic()
2247 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2249 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2256 * @hw: pointer to hardware structure
2267 int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2281 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2282 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2283 hw_dbg(hw, "Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2285 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2286 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2290 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2291 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2294 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2295 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2297 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2298 hw_dbg(hw, "Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2305 * @hw: pointer to hardware structure
2309 static int ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
2320 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
2325 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
2326 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
2328 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
2339 * @hw: pointer to hardware structure
2343 static int ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
2353 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
2357 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
2358 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
2366 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
2367 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
2369 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
2378 * @hw: pointer to hardware structure
2382 static int ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
2387 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_fc_autoneg_copper()
2390 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, in ixgbe_fc_autoneg_copper()
2394 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
2402 * @hw: pointer to hardware structure
2407 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
2422 if (hw->fc.disable_fc_autoneg) in ixgbe_fc_autoneg()
2425 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
2429 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
2433 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
2438 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
2443 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
2444 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
2453 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
2455 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
2456 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
2462 * @hw: pointer to hardware structure
2470 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
2475 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
2509 * @hw: pointer to hardware structure
2516 static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) in ixgbe_disable_pcie_primary() argument
2522 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_primary()
2526 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) in ixgbe_disable_pcie_primary()
2531 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); in ixgbe_disable_pcie_primary()
2536 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_primary()
2537 ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2543 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_primary()
2555 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_primary()
2557 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_primary()
2559 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_primary()
2566 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_primary()
2569 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_primary()
2570 if (ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2576 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); in ixgbe_disable_pcie_primary()
2582 * @hw: pointer to hardware structure
2588 int ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
2601 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
2604 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
2607 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
2608 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2612 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2619 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
2627 * @hw: pointer to hardware structure
2633 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
2638 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2640 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
2642 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
2644 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2649 * @hw: pointer to hardware structure
2656 int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
2659 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
2665 * @hw: pointer to hardware structure
2670 int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
2672 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
2678 * @hw: pointer to hardware structure
2680 * Stops the receive data path and waits for the HW to internally
2683 int ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_buff_generic() argument
2689 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_rx_buff_generic()
2691 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_rx_buff_generic()
2693 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_rx_buff_generic()
2703 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); in ixgbe_disable_rx_buff_generic()
2711 * @hw: pointer to hardware structure
2715 int ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_buff_generic() argument
2719 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_rx_buff_generic()
2721 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_rx_buff_generic()
2722 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_rx_buff_generic()
2729 * @hw: pointer to hardware structure
2734 int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2737 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_generic()
2739 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_generic()
2746 * @hw: pointer to hardware structure
2749 int ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
2751 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_blink_led_start_generic()
2752 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
2765 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
2768 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
2775 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
2779 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2786 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
2787 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2794 * @hw: pointer to hardware structure
2797 int ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
2799 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
2807 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
2814 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
2821 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
2822 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
2829 * @hw: pointer to hardware structure
2836 static int ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
2845 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
2848 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_offset()
2856 * @hw: pointer to hardware structure
2864 int ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
2874 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
2880 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
2882 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
2885 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
2888 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_generic()
2909 * @hw: pointer to hardware structure
2914 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
2920 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
2941 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
2942 if (ixgbe_removed(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
2946 /* MSI-X count is zero-based in HW */ in ixgbe_get_pcie_msix_count_generic()
2957 * @hw: pointer to hardware struct
2961 int ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
2964 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
2968 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_generic()
2972 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
2973 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
2975 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
2983 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
2987 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
2992 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
2995 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
3000 rar != 0 && rar != hw->mac.san_mac_rar_index) in ixgbe_clear_vmdq_generic()
3001 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
3008 * @hw: pointer to hardware struct
3012 int ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
3015 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
3019 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_set_vmdq_generic()
3024 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
3026 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
3028 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
3030 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
3037 * @hw: pointer to hardware struct
3043 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3045 int ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
3047 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
3050 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); in ixgbe_set_vmdq_san_mac_generic()
3051 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3053 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3054 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
3062 * @hw: pointer to hardware structure
3064 int ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
3069 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
3076 * @hw: pointer to hardware structure
3084 static int ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) in ixgbe_find_vlvf_slot() argument
3108 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3119 hw_dbg(hw, "No space in VLVF.\n"); in ixgbe_find_vlvf_slot()
3126 * @hw: pointer to hardware structure
3134 int ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3157 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); in ixgbe_set_vfta_generic()
3174 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) in ixgbe_set_vfta_generic()
3177 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); in ixgbe_set_vfta_generic()
3184 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); in ixgbe_set_vfta_generic()
3195 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { in ixgbe_set_vfta_generic()
3201 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3204 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vfta_generic()
3205 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); in ixgbe_set_vfta_generic()
3228 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); in ixgbe_set_vfta_generic()
3229 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); in ixgbe_set_vfta_generic()
3234 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3241 * @hw: pointer to hardware structure
3245 int ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
3249 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
3250 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
3253 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
3254 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); in ixgbe_clear_vfta_generic()
3255 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); in ixgbe_clear_vfta_generic()
3263 * @hw: pointer to hardware structure
3268 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) in ixgbe_need_crosstalk_fix() argument
3271 if (!hw->need_crosstalk_fix) in ixgbe_need_crosstalk_fix()
3275 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_need_crosstalk_fix()
3288 * @hw: pointer to hardware structure
3295 int ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
3298 bool crosstalk_fix_active = ixgbe_need_crosstalk_fix(hw); in ixgbe_check_mac_link_generic()
3308 switch (hw->mac.type) { in ixgbe_check_mac_link_generic()
3310 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3315 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3332 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3334 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3337 hw_dbg(hw, "LINKS changed from %08X to %08X\n", in ixgbe_check_mac_link_generic()
3350 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3360 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3375 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3385 if ((hw->mac.type >= ixgbe_mac_X550 || in ixgbe_check_mac_link_generic()
3386 hw->mac.type == ixgbe_mac_e610) && in ixgbe_check_mac_link_generic()
3394 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || in ixgbe_check_mac_link_generic()
3395 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { in ixgbe_check_mac_link_generic()
3409 * @hw: pointer to hardware structure
3416 int ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
3428 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
3437 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
3444 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) in ixgbe_get_wwn_prefix_generic()
3445 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3448 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
3454 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3460 * @hw: pointer to hardware structure
3465 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_mac_anti_spoofing() argument
3471 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
3474 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_mac_anti_spoofing()
3479 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3484 * @hw: pointer to hardware structure
3489 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
3495 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
3498 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
3503 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
3508 * @hw: pointer to hardware structure
3514 int ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
3516 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
3523 * @hw: pointer to hardware structure
3528 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, in ixgbe_set_rxpba_generic() argument
3533 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
3555 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3561 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3575 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
3576 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
3581 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3582 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3583 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
3611 * @hw: pointer to the HW structure
3624 int ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, in ixgbe_hic_unlocked() argument
3631 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_hic_unlocked()
3636 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_hic_unlocked()
3637 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_hic_unlocked()
3640 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3642 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); in ixgbe_hic_unlocked()
3648 hw_dbg(hw, "Buffer length failure, not aligned to dword"); in ixgbe_hic_unlocked()
3658 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_hic_unlocked()
3662 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_hic_unlocked()
3665 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3673 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) in ixgbe_hic_unlocked()
3681 * @hw: pointer to the HW structure
3696 int ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, in ixgbe_host_interface_command() argument
3708 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_host_interface_command()
3712 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3716 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); in ixgbe_host_interface_command()
3728 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3738 hw_dbg(hw, "Buffer not large enough for reply message.\n"); in ixgbe_host_interface_command()
3748 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3753 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3760 * @hw: pointer to the HW structure
3773 int ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
3784 fw_cmd.port_num = hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
3796 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, in ixgbe_set_fw_drv_ver_generic()
3817 * @hw: pointer to the hardware structure
3823 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
3832 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
3840 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
3841 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
3844 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3850 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
3853 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
3854 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_tx_pending()
3861 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
3862 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
3866 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3870 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
3871 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
3889 * @hw: pointer to hardware structure
3895 static int ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, in ixgbe_get_ets_data() argument
3900 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); in ixgbe_get_ets_data()
3907 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); in ixgbe_get_ets_data()
3919 * @hw: pointer to hardware structure
3923 int ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
3931 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
3934 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_get_thermal_sensor_data_generic()
3937 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
3949 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
3960 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
3974 * @hw: pointer to hardware structure
3979 int ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
3981 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
3994 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
3997 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_init_thermal_sensor_thresh_generic()
4010 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
4011 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_init_thermal_sensor_thresh_generic()
4021 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
4039 * @hw: pointer to hardware structure
4045 void ixgbe_get_orom_version(struct ixgbe_hw *hw, in ixgbe_get_orom_version() argument
4052 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); in ixgbe_get_orom_version()
4058 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); in ixgbe_get_orom_version()
4059 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); in ixgbe_get_orom_version()
4076 * @hw: pointer to hardware structure
4082 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, in ixgbe_get_oem_prod_version() argument
4088 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); in ixgbe_get_oem_prod_version()
4095 hw->eeprom.ops.read(hw, offset, &mod_len); in ixgbe_get_oem_prod_version()
4096 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); in ixgbe_get_oem_prod_version()
4103 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); in ixgbe_get_oem_prod_version()
4104 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); in ixgbe_get_oem_prod_version()
4120 * @hw: pointer to hardware structure
4125 void ixgbe_get_etk_id(struct ixgbe_hw *hw, in ixgbe_get_etk_id() argument
4130 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) in ixgbe_get_etk_id()
4132 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) in ixgbe_get_etk_id()
4147 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
4151 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
4153 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
4156 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
4159 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
4160 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
4162 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
4166 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
4170 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
4174 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
4175 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
4177 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
4178 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
4181 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
4183 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
4184 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
4190 * @hw: pointer to hardware structure
4192 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
4196 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
4199 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_present()
4206 * @hw: pointer to hardware structure
4212 int ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
4224 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
4238 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4240 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4247 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4254 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4261 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4262 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4273 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
4289 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4291 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4298 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4305 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4312 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4313 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4319 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4333 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4339 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
4342 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4345 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4352 * @hw: pointer to hardware structure
4357 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
4372 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_soft_rate_select_speed()
4377 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4381 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4387 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4391 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4396 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4400 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()
4406 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4410 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()