Lines Matching full:sparx5
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
36 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb() local
37 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
51 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
56 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
58 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_rx_activate()
65 sparx5, FDMA_CH_CFG(fdma->channel_id)); in sparx5_fdma_rx_activate()
69 sparx5, in sparx5_fdma_rx_activate()
74 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
79 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_activate()
82 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
85 static void sparx5_fdma_rx_deactivate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_deactivate() argument
91 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_deactivate()
95 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_deactivate()
99 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_deactivate()
102 static void sparx5_fdma_tx_activate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_activate() argument
107 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
109 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_tx_activate()
116 sparx5, FDMA_CH_CFG(fdma->channel_id)); in sparx5_fdma_tx_activate()
120 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_tx_activate()
123 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
126 static void sparx5_fdma_tx_deactivate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_deactivate() argument
130 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_deactivate()
133 void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) in sparx5_fdma_reload() argument
136 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_reload()
139 static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_get_frame() argument
154 sparx5_ifh_parse(sparx5, (u32 *)skb->data, &fi); in sparx5_fdma_rx_get_frame()
156 port = fi.src_port < sparx5->data->consts->n_ports ? in sparx5_fdma_rx_get_frame()
157 sparx5->ports[fi.src_port] : in sparx5_fdma_rx_get_frame()
160 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); in sparx5_fdma_rx_get_frame()
161 sparx5_xtr_flush(sparx5, XTR_QUEUE); in sparx5_fdma_rx_get_frame()
169 sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp); in sparx5_fdma_rx_get_frame()
174 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_fdma_rx_get_frame()
186 struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); in sparx5_fdma_napi_callback() local
190 while (counter < weight && sparx5_fdma_rx_get_frame(sparx5, rx)) { in sparx5_fdma_napi_callback()
206 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_napi_callback()
209 sparx5_fdma_reload(sparx5, fdma); in sparx5_fdma_napi_callback()
213 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, in sparx5_fdma_xmit() argument
216 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_xmit()
238 sparx5_fdma_reload(sparx5, fdma); in sparx5_fdma_xmit()
243 static int sparx5_fdma_rx_alloc(struct sparx5 *sparx5) in sparx5_fdma_rx_alloc() argument
245 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_alloc()
259 static int sparx5_fdma_tx_alloc(struct sparx5 *sparx5) in sparx5_fdma_tx_alloc() argument
261 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_tx_alloc()
275 static void sparx5_fdma_rx_init(struct sparx5 *sparx5, in sparx5_fdma_rx_init() argument
284 fdma->priv = sparx5; in sparx5_fdma_rx_init()
286 fdma->size = fdma_get_size(&sparx5->rx.fdma); in sparx5_fdma_rx_init()
290 for (idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { in sparx5_fdma_rx_init()
291 struct sparx5_port *port = sparx5->ports[idx]; in sparx5_fdma_rx_init()
300 static void sparx5_fdma_tx_init(struct sparx5 *sparx5, in sparx5_fdma_tx_init() argument
308 fdma->priv = sparx5; in sparx5_fdma_tx_init()
310 fdma->size = fdma_get_size_contiguous(&sparx5->tx.fdma); in sparx5_fdma_tx_init()
317 struct sparx5 *sparx5 = args; in sparx5_fdma_handler() local
320 db = spx5_rd(sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
321 err = spx5_rd(sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
324 spx5_wr(0, sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_handler()
325 spx5_wr(db, sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
326 napi_schedule(&sparx5->rx.napi); in sparx5_fdma_handler()
329 u32 err_type = spx5_rd(sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
331 dev_err_ratelimited(sparx5->dev, in sparx5_fdma_handler()
334 spx5_wr(err, sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
335 spx5_wr(err_type, sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
340 void sparx5_fdma_injection_mode(struct sparx5 *sparx5) in sparx5_fdma_injection_mode() argument
350 sparx5, QS_XTR_GRP_CFG(XTR_QUEUE)); in sparx5_fdma_injection_mode()
353 sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); in sparx5_fdma_injection_mode()
356 for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); in sparx5_fdma_injection_mode()
357 portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); in sparx5_fdma_injection_mode()
363 sparx5, ASM_PORT_CFG(portno)); in sparx5_fdma_injection_mode()
368 sparx5, in sparx5_fdma_injection_mode()
374 sparx5, in sparx5_fdma_injection_mode()
378 urgency = sparx5_port_fwd_urg(sparx5, SPEED_2500); in sparx5_fdma_injection_mode()
383 sparx5, in sparx5_fdma_injection_mode()
391 sparx5, in sparx5_fdma_injection_mode()
397 sparx5, in sparx5_fdma_injection_mode()
402 int sparx5_fdma_init(struct sparx5 *sparx5) in sparx5_fdma_init() argument
407 spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); in sparx5_fdma_init()
408 spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); in sparx5_fdma_init()
417 sparx5, CPU_PROC_CTRL); in sparx5_fdma_init()
419 sparx5_fdma_injection_mode(sparx5); in sparx5_fdma_init()
420 sparx5_fdma_rx_init(sparx5, &sparx5->rx, FDMA_XTR_CHANNEL); in sparx5_fdma_init()
421 sparx5_fdma_tx_init(sparx5, &sparx5->tx, FDMA_INJ_CHANNEL); in sparx5_fdma_init()
422 err = sparx5_fdma_rx_alloc(sparx5); in sparx5_fdma_init()
424 dev_err(sparx5->dev, "Could not allocate RX buffers: %d\n", err); in sparx5_fdma_init()
427 err = sparx5_fdma_tx_alloc(sparx5); in sparx5_fdma_init()
429 dev_err(sparx5->dev, "Could not allocate TX buffers: %d\n", err); in sparx5_fdma_init()
435 int sparx5_fdma_deinit(struct sparx5 *sparx5) in sparx5_fdma_deinit() argument
437 sparx5_fdma_stop(sparx5); in sparx5_fdma_deinit()
438 fdma_free_phys(&sparx5->rx.fdma); in sparx5_fdma_deinit()
439 fdma_free_phys(&sparx5->tx.fdma); in sparx5_fdma_deinit()
444 static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5) in sparx5_fdma_port_ctrl() argument
446 return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_port_ctrl()
449 int sparx5_fdma_start(struct sparx5 *sparx5) in sparx5_fdma_start() argument
451 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_fdma_start()
452 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_start()
453 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_start()
462 sparx5_fdma_rx_activate(sparx5, rx); in sparx5_fdma_start()
463 sparx5_fdma_tx_activate(sparx5, tx); in sparx5_fdma_start()
468 int sparx5_fdma_stop(struct sparx5 *sparx5) in sparx5_fdma_stop() argument
470 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_stop()
471 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_stop()
477 sparx5_fdma_rx_deactivate(sparx5, rx); in sparx5_fdma_stop()
478 sparx5_fdma_tx_deactivate(sparx5, tx); in sparx5_fdma_stop()
483 500, 10000, 0, sparx5); in sparx5_fdma_stop()