2 /* Microchip Sparx5 Switch driver
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp)  in sparx5_xtr_flush()  argument
26 	spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH);  in sparx5_xtr_flush()
32 	spx5_wr(0, sparx5, QS_XTR_FLUSH);  in sparx5_xtr_flush()
35 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info)  in sparx5_ifh_parse()  argument
46 	info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1),  in sparx5_ifh_parse()
60 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap)  in sparx5_xtr_grp()  argument
73 		ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
76 	sparx5_ifh_parse(sparx5, ifh, &fi);  in sparx5_xtr_grp()
79 	port = fi.src_port < sparx5->data->consts->n_ports ?  in sparx5_xtr_grp()
80 		sparx5->ports[fi.src_port] : NULL;  in sparx5_xtr_grp()
82 		dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port);  in sparx5_xtr_grp()
83 		sparx5_xtr_flush(sparx5, grp);  in sparx5_xtr_grp()
91 		sparx5_xtr_flush(sparx5, grp);  in sparx5_xtr_grp()
92 		dev_err(sparx5->dev, "No skb allocated\n");  in sparx5_xtr_grp()
100 		u32 val = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
132 			*rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp));  in sparx5_xtr_grp()
154 	if (test_bit(port->portno, sparx5->bridge_mask))  in sparx5_xtr_grp()
160 	sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);  in sparx5_xtr_grp()
167 static int sparx5_inject(struct sparx5 *sparx5,  in sparx5_inject()  argument
176 	val = spx5_rd(sparx5, QS_INJ_STATUS);  in sparx5_inject()
186 		sparx5, QS_INJ_CTRL(grp));  in sparx5_inject()
190 		spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp));  in sparx5_inject()
197 		spx5_wr(val, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
202 		spx5_wr(0, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
210 		sparx5, QS_INJ_CTRL(grp));  in sparx5_inject()
213 	spx5_wr(0, sparx5, QS_INJ_WR(grp));  in sparx5_inject()
216 	val = spx5_rd(sparx5, QS_INJ_STATUS);  in sparx5_inject()
234 	struct sparx5 *sparx5 = port->sparx5;  in sparx5_port_xmit_impl()  local
239 	ops = sparx5->data->ops;  in sparx5_port_xmit_impl()
242 	sparx5_set_port_ifh(sparx5, ifh, port->portno);  in sparx5_port_xmit_impl()
244 	if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {  in sparx5_port_xmit_impl()
249 		sparx5_set_port_ifh_pdu_type(sparx5, ifh,  in sparx5_port_xmit_impl()
251 		sparx5_set_port_ifh_pdu_w16_offset(sparx5, ifh,  in sparx5_port_xmit_impl()
253 		sparx5_set_port_ifh_timestamp(sparx5, ifh,  in sparx5_port_xmit_impl()
258 	spin_lock(&sparx5->tx_lock);  in sparx5_port_xmit_impl()
259 	if (sparx5->fdma_irq > 0)  in sparx5_port_xmit_impl()
260 		ret = ops->fdma_xmit(sparx5, ifh, skb, dev);  in sparx5_port_xmit_impl()
262 		ret = sparx5_inject(sparx5, ifh, skb, dev);  in sparx5_port_xmit_impl()
263 	spin_unlock(&sparx5->tx_lock);  in sparx5_port_xmit_impl()
270 	if (!is_sparx5(sparx5))  in sparx5_port_xmit_impl()
278 	sparx5->tx.packets++;  in sparx5_port_xmit_impl()
288 	sparx5->tx.dropped++;  in sparx5_port_xmit_impl()
305 	val = spx5_rd(port->sparx5, QS_INJ_STATUS);  in sparx5_injection_timeout()
311 			 port->sparx5,  in sparx5_injection_timeout()
318 int sparx5_manual_injection_mode(struct sparx5 *sparx5)  in sparx5_manual_injection_mode()  argument
327 		sparx5, QS_XTR_GRP_CFG(XTR_QUEUE));  in sparx5_manual_injection_mode()
330 		sparx5, QS_INJ_GRP_CFG(INJ_QUEUE));  in sparx5_manual_injection_mode()
333 	for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0);  in sparx5_manual_injection_mode()
334 	     portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1);  in sparx5_manual_injection_mode()
340 			sparx5, ASM_PORT_CFG(portno));  in sparx5_manual_injection_mode()
345 			 sparx5,  in sparx5_manual_injection_mode()
351 			 sparx5,  in sparx5_manual_injection_mode()
358 			 sparx5,  in sparx5_manual_injection_mode()
366 	struct sparx5 *s5 = _sparx5;  in sparx5_xtr_handler()