Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
57 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
67 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
69 #define GMAC_RXQCTRL_TACPQE BIT(21)
74 #define GMAC_PACKET_FILTER_PR BIT(0)
75 #define GMAC_PACKET_FILTER_HMC BIT(2)
76 #define GMAC_PACKET_FILTER_PM BIT(4)
77 #define GMAC_PACKET_FILTER_PCF BIT(7)
78 #define GMAC_PACKET_FILTER_HPF BIT(10)
79 #define GMAC_PACKET_FILTER_VTFE BIT(16)
80 #define GMAC_PACKET_FILTER_IPFE BIT(20)
81 #define GMAC_PACKET_FILTER_RA BIT(31)
86 #define GMAC_VLAN_EDVLP BIT(26)
87 #define GMAC_VLAN_VTHM BIT(25)
88 #define GMAC_VLAN_DOVLTC BIT(20)
89 #define GMAC_VLAN_ESVL BIT(18)
90 #define GMAC_VLAN_ETV BIT(16)
92 #define GMAC_VLAN_VLTI BIT(20)
93 #define GMAC_VLAN_CSVL BIT(19)
100 #define GMAC_VLAN_TAG_ETV BIT(16)
103 #define GMAC_VLAN_TAG_CTRL_OB BIT(0)
104 #define GMAC_VLAN_TAG_CTRL_CT BIT(1)
105 #define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)
106 #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2
109 #define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24)
118 #define GMAC_VLAN_TAG_DATA_VEN BIT(16)
119 #define GMAC_VLAN_TAG_DATA_ETV BIT(17)
122 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
123 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
124 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
127 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
138 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
142 #define GMAC_INT_RGSMIIS BIT(0)
143 #define GMAC_INT_PCS_LINK BIT(1)
144 #define GMAC_INT_PCS_ANE BIT(2)
145 #define GMAC_INT_PCS_PHYIS BIT(3)
146 #define GMAC_INT_PMT_EN BIT(4)
147 #define GMAC_INT_LPI_EN BIT(5)
148 #define GMAC_INT_TSIE BIT(12)
187 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
188 #define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
189 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
190 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
191 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
192 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
193 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
194 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
195 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
202 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
204 #define GMAC_DEBUG_TPESTS BIT(16)
205 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
207 #define GMAC_DEBUG_RPESTS BIT(0)
210 #define GMAC_CONFIG_ARPEN BIT(31)
213 #define GMAC_CONFIG_IPC BIT(27)
216 #define GMAC_CONFIG_2K BIT(22)
217 #define GMAC_CONFIG_ACS BIT(20)
218 #define GMAC_CONFIG_BE BIT(18)
219 #define GMAC_CONFIG_JD BIT(17)
220 #define GMAC_CONFIG_JE BIT(16)
221 #define GMAC_CONFIG_PS BIT(15)
222 #define GMAC_CONFIG_FES BIT(14)
224 #define GMAC_CONFIG_DM BIT(13)
225 #define GMAC_CONFIG_LM BIT(12)
226 #define GMAC_CONFIG_DCRS BIT(9)
227 #define GMAC_CONFIG_TE BIT(1)
228 #define GMAC_CONFIG_RE BIT(0)
233 #define GMAC_CONFIG_EIPG_EN BIT(24)
239 #define GMAC_HW_FEAT_SAVLANINS BIT(27)
240 #define GMAC_HW_FEAT_ADDMAC BIT(18)
241 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
242 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
243 #define GMAC_HW_FEAT_EEESEL BIT(13)
244 #define GMAC_HW_FEAT_TSSEL BIT(12)
245 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
246 #define GMAC_HW_FEAT_MMCSEL BIT(8)
247 #define GMAC_HW_FEAT_MGKSEL BIT(7)
248 #define GMAC_HW_FEAT_RWKSEL BIT(6)
249 #define GMAC_HW_FEAT_SMASEL BIT(5)
250 #define GMAC_HW_FEAT_VLHASH BIT(4)
251 #define GMAC_HW_FEAT_PCSSEL BIT(3)
252 #define GMAC_HW_FEAT_HDSEL BIT(2)
253 #define GMAC_HW_FEAT_GMIISEL BIT(1)
254 #define GMAC_HW_FEAT_MIISEL BIT(0)
259 #define GMAC_HW_FEAT_AVSEL BIT(20)
260 #define GMAC_HW_TSOEN BIT(18)
261 #define GMAC_HW_FEAT_SPHEN BIT(17)
276 #define GMAC_HW_FEAT_TBSSEL BIT(27)
277 #define GMAC_HW_FEAT_FPESEL BIT(26)
280 #define GMAC_HW_FEAT_ESTSEL BIT(16)
283 #define GMAC_HW_FEAT_FRPSEL BIT(10)
284 #define GMAC_HW_FEAT_DVLAN BIT(5)
285 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
288 #define GMAC_CONFIG1_SAVE_EN BIT(24)
292 #define GMAC_GPO0 BIT(16)
293 #define GMAC_GPO1 BIT(17)
294 #define GMAC_GPO2 BIT(18)
295 #define GMAC_GPO3 BIT(19)
300 #define GMAC_HI_REG_AE BIT(31)
303 #define GMAC_L4DPIM0 BIT(21)
304 #define GMAC_L4DPM0 BIT(20)
305 #define GMAC_L4SPIM0 BIT(19)
306 #define GMAC_L4SPM0 BIT(18)
307 #define GMAC_L4PEN0 BIT(16)
308 #define GMAC_L3DAIM0 BIT(5)
309 #define GMAC_L3DAM0 BIT(4)
310 #define GMAC_L3SAIM0 BIT(3)
311 #define GMAC_L3SAM0 BIT(2)
312 #define GMAC_L3PEN0 BIT(0)
318 #define GMAC_TIMESTAMP_AUXTSTRIG BIT(2)
324 #define MTL_FRPE BIT(15)
330 #define MTL_OPERATION_RAA BIT(2)
331 #define MTL_OPERATION_RAA_SP (0x0 << 2)
332 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
335 #define MTL_INT_QX(x) BIT(x)
351 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset); in mtl_chanx_base_addr()
364 #define MTL_OP_MODE_RSF BIT(5)
365 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
366 #define MTL_OP_MODE_TXQEN_AV BIT(2)
367 #define MTL_OP_MODE_TXQEN BIT(3)
368 #define MTL_OP_MODE_TSF BIT(1)
378 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
394 #define MTL_OP_MODE_EHFC BIT(7)
401 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
414 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset); in mtl_etsx_ctrl_base_addr()
421 #define MTL_ETS_CTRL_CC BIT(3)
422 #define MTL_ETS_CTRL_AVALG BIT(2)
434 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset); in mtl_txqx_weight_base_addr()
453 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset); in mtl_send_slp_credx_base_addr()
472 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset); in mtl_high_credx_base_addr()
491 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset); in mtl_low_credx_base_addr()
501 #define MTL_DEBUG_TXSTSFSTS BIT(5)
502 #define MTL_DEBUG_TXFSTS BIT(4)
503 #define MTL_DEBUG_TWCSTS BIT(3)
506 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
510 #define MTL_DEBUG_TRCSTS_TXW 2
512 #define MTL_DEBUG_TXPAUSED BIT(0)
519 #define MTL_DEBUG_RXFSTS_AT 2
521 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
525 #define MTL_DEBUG_RRCSTS_RSTAT 2
527 #define MTL_DEBUG_RWCSTS BIT(0)
530 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
531 #define MTL_RX_OVERFLOW_INT BIT(16)
542 #define MTL_DEBUG_TXSTSFSTS BIT(5)
543 #define MTL_DEBUG_TXFSTS BIT(4)
544 #define MTL_DEBUG_TWCSTS BIT(3)
547 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
551 #define MTL_DEBUG_TRCSTS_TXW 2
553 #define MTL_DEBUG_TXPAUSED BIT(0)
560 #define MTL_DEBUG_RXFSTS_AT 2
562 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
566 #define MTL_DEBUG_RRCSTS_RSTAT 2
568 #define MTL_DEBUG_RWCSTS BIT(0)
571 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
572 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
573 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
574 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
577 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
578 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
579 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)