Lines Matching +full:0 +full:x3d00
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ee_stop_tx_beacon()
44 tmp &= ~(BIT(0)); in _rtl92ee_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ee_resume_tx_beacon()
57 tmp |= BIT(0); in _rtl92ee_resume_tx_beacon()
63 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ee_enable_bcn_sub_func()
68 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ee_disable_bcn_sub_func()
77 u32 count = 0, isr_regaddr, content; in _rtl92ee_set_fw_clock_on()
120 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); in _rtl92ee_set_fw_clock_on()
163 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { in _rtl92ee_set_fw_clock_off()
183 rtl_write_word(rtlpriv, REG_HISR, 0x0100); in _rtl92ee_set_fw_clock_off()
199 u8 rpwm_val = 0; in _rtl92ee_set_fw_ps_rf_on()
207 u8 rpwm_val = 0; in _rtl92ee_set_fw_ps_rf_off_low_power()
226 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; in _rtl92ee_fwlps_leave()
297 val_rcr &= 0x00070000; in rtl92ee_get_hw_reg()
333 u8 count = 0, dlbcn_count = 0; in _rtl92ee_download_rsvd_page()
338 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0)); in _rtl92ee_download_rsvd_page()
345 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); in _rtl92ee_download_rsvd_page()
346 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); in _rtl92ee_download_rsvd_page()
348 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to in _rtl92ee_download_rsvd_page()
361 bcnvalid_reg | BIT(0)); in _rtl92ee_download_rsvd_page()
367 count = 0; in _rtl92ee_download_rsvd_page()
378 count = 0; in _rtl92ee_download_rsvd_page()
379 while (!(bcnvalid_reg & BIT(0)) && count < 20) { in _rtl92ee_download_rsvd_page()
386 if (bcnvalid_reg & BIT(0)) in _rtl92ee_download_rsvd_page()
387 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0)); in _rtl92ee_download_rsvd_page()
390 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); in _rtl92ee_download_rsvd_page()
392 if (!(bcnvalid_reg & BIT(0))) in _rtl92ee_download_rsvd_page()
397 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); in _rtl92ee_download_rsvd_page()
398 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); in _rtl92ee_download_rsvd_page()
404 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0))); in _rtl92ee_download_rsvd_page()
418 for (idx = 0; idx < ETH_ALEN; idx++) in rtl92ee_set_hw_reg()
422 u16 b_rate_cfg = ((u16 *)val)[0]; in rtl92ee_set_hw_reg()
424 b_rate_cfg = b_rate_cfg & 0x15f; in rtl92ee_set_hw_reg()
425 b_rate_cfg |= 0x01; in rtl92ee_set_hw_reg()
426 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1)); in rtl92ee_set_hw_reg()
427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); in rtl92ee_set_hw_reg()
428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff); in rtl92ee_set_hw_reg()
431 for (idx = 0; idx < ETH_ALEN; idx++) in rtl92ee_set_hw_reg()
435 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92ee_set_hw_reg()
438 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92ee_set_hw_reg()
439 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92ee_set_hw_reg()
442 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e); in rtl92ee_set_hw_reg()
451 "HW_VAR_SLOT_TIME %x\n", val[0]); in rtl92ee_set_hw_reg()
453 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92ee_set_hw_reg()
455 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { in rtl92ee_set_hw_reg()
466 reg_tmp |= 0x80; in rtl92ee_set_hw_reg()
475 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; in rtl92ee_set_hw_reg()
478 u8 i = 0; in rtl92ee_set_hw_reg()
485 if (fac > 0xf) in rtl92ee_set_hw_reg()
486 fac = 0xf; in rtl92ee_set_hw_reg()
487 for (i = 0; i < 4; i++) { in rtl92ee_set_hw_reg()
488 if ((reg[i] & 0xf0) > (fac << 4)) in rtl92ee_set_hw_reg()
489 reg[i] = (reg[i] & 0x0f) | in rtl92ee_set_hw_reg()
491 if ((reg[i] & 0x0f) > fac) in rtl92ee_set_hw_reg()
492 reg[i] = (reg[i] & 0xf0) | fac; in rtl92ee_set_hw_reg()
512 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs); in rtl92ee_set_hw_reg()
517 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92ee_set_hw_reg()
556 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92ee_set_hw_reg()
562 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); in rtl92ee_set_hw_reg()
563 rtlpci->receive_config = ((u32 *)(val))[0]; in rtl92ee_set_hw_reg()
567 u8 retry_limit = ((u8 *)(val))[0]; in rtl92ee_set_hw_reg()
575 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92ee_set_hw_reg()
635 u2btmp &= 0xC000; in rtl92ee_set_hw_reg()
641 u8 btype_ibss = ((u8 *)(val))[0]; in rtl92ee_set_hw_reg()
646 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92ee_set_hw_reg()
649 (u32)(mac->tsf & 0xffffffff)); in rtl92ee_set_hw_reg()
651 (u32)((mac->tsf >> 32) & 0xffffffff)); in rtl92ee_set_hw_reg()
653 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92ee_set_hw_reg()
662 array[0] = 0xff; in rtl92ee_set_hw_reg()
678 u8 u8tmp, testcnt = 0; in _rtl92ee_llt_table_init()
680 txpktbuf_bndy = 0xF7; in _rtl92ee_llt_table_init()
682 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E60808); in _rtl92ee_llt_table_init()
685 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1); in _rtl92ee_llt_table_init()
694 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92ee_llt_table_init()
696 rtl_write_byte(rtlpriv, REG_PBP, 0x31); in _rtl92ee_llt_table_init()
697 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92ee_llt_table_init()
700 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0)); in _rtl92ee_llt_table_init()
702 while (u8tmp & BIT(0)) { in _rtl92ee_llt_table_init()
740 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); in _rtl92ee_init_mac()
744 rtl_write_byte(rtlpriv, 0x7c, 0xc3); in _rtl92ee_init_mac()
746 bytetmp = rtl_read_byte(rtlpriv, 0x16); in _rtl92ee_init_mac()
747 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6)); in _rtl92ee_init_mac()
748 rtl_write_byte(rtlpriv, 0x7c, 0x83); in _rtl92ee_init_mac()
752 bytetmp &= 0xfb; in _rtl92ee_init_mac()
756 dwordtmp &= 0xfffffc7f; in _rtl92ee_init_mac()
763 bytetmp &= 0xbf; in _rtl92ee_init_mac()
767 dwordtmp &= 0xffdfffff; in _rtl92ee_init_mac()
781 bytetmp = 0xff; in _rtl92ee_init_mac()
784 bytetmp = 0x7f; in _rtl92ee_init_mac()
794 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92ee_init_mac()
804 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92ee_init_mac()
805 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); in _rtl92ee_init_mac()
808 wordtmp &= 0xf; in _rtl92ee_init_mac()
809 wordtmp |= 0xF5B1; in _rtl92ee_init_mac()
812 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92ee_init_mac()
816 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); in _rtl92ee_init_mac()
881 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff); in _rtl92ee_init_mac()
884 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7); in _rtl92ee_init_mac()
886 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92ee_init_mac()
888 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92ee_init_mac()
891 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
893 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
895 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
897 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
899 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
901 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
903 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
905 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
907 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
909 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
911 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
913 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
915 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
917 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); in _rtl92ee_init_mac()
921 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000); in _rtl92ee_init_mac()
923 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF); in _rtl92ee_init_mac()
940 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010); in _rtl92ee_hw_configure()
941 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000); in _rtl92ee_hw_configure()
944 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010); in _rtl92ee_hw_configure()
945 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000); in _rtl92ee_hw_configure()
948 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92ee_hw_configure()
951 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92ee_hw_configure()
954 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707); in _rtl92ee_hw_configure()
957 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff); in _rtl92ee_hw_configure()
960 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92ee_hw_configure()
961 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92ee_hw_configure()
962 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92ee_hw_configure()
963 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92ee_hw_configure()
966 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92ee_hw_configure()
967 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92ee_hw_configure()
969 rtlpci->reg_bcn_ctrl_val = 0x1d; in _rtl92ee_hw_configure()
977 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0); in _rtl92ee_hw_configure()
980 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */ in _rtl92ee_hw_configure()
982 rtl_write_byte(rtlpriv, REG_PIFS, 0); in _rtl92ee_hw_configure()
983 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92ee_hw_configure()
985 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); in _rtl92ee_hw_configure()
986 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff); in _rtl92ee_hw_configure()
989 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); in _rtl92ee_hw_configure()
992 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92ee_hw_configure()
995 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a); in _rtl92ee_hw_configure()
996 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a); in _rtl92ee_hw_configure()
999 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a); in _rtl92ee_hw_configure()
1002 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a); in _rtl92ee_hw_configure()
1005 rtl_write_byte(rtlpriv, 0x4C7, 0x80); in _rtl92ee_hw_configure()
1007 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); in _rtl92ee_hw_configure()
1009 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717); in _rtl92ee_hw_configure()
1012 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92ee_hw_configure()
1013 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92ee_hw_configure()
1020 u32 tmp32 = 0, count = 0; in _rtl92ee_enable_aspm_back_door()
1021 u8 tmp8 = 0; in _rtl92ee_enable_aspm_back_door()
1023 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78); in _rtl92ee_enable_aspm_back_door()
1024 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1026 count = 0; in _rtl92ee_enable_aspm_back_door()
1033 if (0 == tmp8) { in _rtl92ee_enable_aspm_back_door()
1035 if ((tmp32 & 0xff00) != 0x2000) { in _rtl92ee_enable_aspm_back_door()
1036 tmp32 &= 0xffff00ff; in _rtl92ee_enable_aspm_back_door()
1039 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078); in _rtl92ee_enable_aspm_back_door()
1040 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1044 count = 0; in _rtl92ee_enable_aspm_back_door()
1054 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c); in _rtl92ee_enable_aspm_back_door()
1055 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1057 count = 0; in _rtl92ee_enable_aspm_back_door()
1063 if (0 == tmp8) { in _rtl92ee_enable_aspm_back_door()
1067 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c); in _rtl92ee_enable_aspm_back_door()
1068 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1072 count = 0; in _rtl92ee_enable_aspm_back_door()
1079 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718); in _rtl92ee_enable_aspm_back_door()
1080 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1082 count = 0; in _rtl92ee_enable_aspm_back_door()
1088 if (ppsc->support_backdoor || (0 == tmp8)) { in _rtl92ee_enable_aspm_back_door()
1092 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718); in _rtl92ee_enable_aspm_back_door()
1093 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1096 count = 0; in _rtl92ee_enable_aspm_back_door()
1143 /* write reg 0x350 Bit[26]=1. Enable debug port. */ in _rtl8192ee_check_pcie_dma_hang()
1151 /* read reg 0x350 Bit[25] if 1 : RX hang in _rtl8192ee_check_pcie_dma_hang()
1152 * read reg 0x350 Bit[24] if 1 : TX hang in _rtl8192ee_check_pcie_dma_hang()
1155 if ((tmp & BIT(0)) || (tmp & BIT(1))) { in _rtl8192ee_check_pcie_dma_hang()
1178 * write 0x1C bit[1:0] = 2'h0 in _rtl8192ee_reset_pcie_interface_dma()
1179 * write 0xCC bit[2] = 1'b1 in _rtl8192ee_reset_pcie_interface_dma()
1182 tmp &= ~(BIT(1) | BIT(0)); in _rtl8192ee_reset_pcie_interface_dma()
1189 * write 0x284 bit[18] = 1'b1 in _rtl8192ee_reset_pcie_interface_dma()
1190 * write 0x301 = 0xFF in _rtl8192ee_reset_pcie_interface_dma()
1202 if (backup_pcie_dma_pause != 0xFF) in _rtl8192ee_reset_pcie_interface_dma()
1203 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); in _rtl8192ee_reset_pcie_interface_dma()
1207 * write 0x100 = 0x00 in _rtl8192ee_reset_pcie_interface_dma()
1209 rtl_write_byte(rtlpriv, REG_CR, 0); in _rtl8192ee_reset_pcie_interface_dma()
1213 * write 0x003 bit[0] = 0 in _rtl8192ee_reset_pcie_interface_dma()
1216 tmp &= ~(BIT(0)); in _rtl8192ee_reset_pcie_interface_dma()
1220 * write 0x003 bit[0] = 1 in _rtl8192ee_reset_pcie_interface_dma()
1223 tmp |= BIT(0); in _rtl8192ee_reset_pcie_interface_dma()
1228 * write 0x100 = 0xFF in _rtl8192ee_reset_pcie_interface_dma()
1230 rtl_write_byte(rtlpriv, REG_CR, 0xFF); in _rtl8192ee_reset_pcie_interface_dma()
1239 * write 0xF8 bit[17] = 1'b1 in _rtl8192ee_reset_pcie_interface_dma()
1252 * write 0x284 bit[18] = 1'b0 in _rtl8192ee_reset_pcie_interface_dma()
1253 * write 0x301 = 0x00 in _rtl8192ee_reset_pcie_interface_dma()
1265 * write 0xCC bit[2] = 1'b0 in _rtl8192ee_reset_pcie_interface_dma()
1280 int err = 0; in rtl92ee_hw_init()
1290 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { in rtl92ee_hw_init()
1306 rtl_write_byte(rtlpriv, 0x577, 0x03); in rtl92ee_hw_init()
1309 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A); in rtl92ee_hw_init()
1310 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00); in rtl92ee_hw_init()
1311 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83); in rtl92ee_hw_init()
1315 rtl_write_byte(rtlpriv, 0x64, 0); in rtl92ee_hw_init()
1316 rtl_write_byte(rtlpriv, 0x65, 1); in rtl92ee_hw_init()
1323 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000); in rtl92ee_hw_init()
1338 rtlhal->last_hmeboxnum = 0; in rtl92ee_hw_init()
1346 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A, in rtl92ee_hw_init()
1352 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | in rtl92ee_hw_init()
1356 rtlphy->rfreg_chnlval[0]); in rtl92ee_hw_init()
1358 rtlphy->rfreg_chnlval[0]); in rtl92ee_hw_init()
1361 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92ee_hw_init()
1362 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92ee_hw_init()
1367 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418); in rtl92ee_hw_init()
1396 rtlphy->rfpath_rx_enable[0] = true; in rtl92ee_hw_init()
1400 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b); in rtl92ee_hw_init()
1401 if (!(tmp_u1b & BIT(0))) { in rtl92ee_hw_init()
1402 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); in rtl92ee_hw_init()
1407 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); in rtl92ee_hw_init()
1415 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75); in rtl92ee_hw_init()
1416 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12); in rtl92ee_hw_init()
1421 rtl_write_dword(rtlpriv, 0x4fc, 0); in rtl92ee_hw_init()
1425 return 0; in rtl92ee_hw_init()
1454 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; in _rtl92ee_set_media_status()
1513 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92ee_set_media_status()
1515 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92ee_set_media_status()
1516 return 0; in _rtl92ee_set_media_status()
1532 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92ee_set_check_bssid()
1535 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92ee_set_check_bssid()
1556 return 0; in rtl92ee_set_network_type()
1567 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); in rtl92ee_set_qos()
1573 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); in rtl92ee_set_qos()
1576 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); in rtl92ee_set_qos()
1589 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1590 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1619 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92ee_poweroff_adapter()
1630 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92ee_poweroff_adapter()
1638 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); in _rtl92ee_poweroff_adapter()
1640 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); in _rtl92ee_poweroff_adapter()
1643 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); in _rtl92ee_poweroff_adapter()
1679 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92ee_interrupt_recognized()
1698 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92ee_set_beacon_related_registers()
1699 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); in rtl92ee_set_beacon_related_registers()
1700 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); in rtl92ee_set_beacon_related_registers()
1701 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92ee_set_beacon_related_registers()
1727 rtlpci->irq_mask[0] |= add_msr; in rtl92ee_update_interrupt_mask()
1729 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92ee_update_interrupt_mask()
1736 u8 group = 0; in _rtl92ee_get_chnl_group()
1740 group = 0; in _rtl92ee_get_chnl_group()
1751 group = 0; in _rtl92ee_get_chnl_group()
1788 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0; in _rtl8192ee_read_power_value_fromprom()
1791 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n", in _rtl8192ee_read_power_value_fromprom()
1793 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/ in _rtl8192ee_read_power_value_fromprom()
1799 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { in _rtl8192ee_read_power_value_fromprom()
1801 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { in _rtl8192ee_read_power_value_fromprom()
1802 pwr2g->index_cck_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1803 pwr2g->index_bw40_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1805 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl8192ee_read_power_value_fromprom()
1806 if (i == 0) { in _rtl8192ee_read_power_value_fromprom()
1807 pwr2g->bw20_diff[rf][0] = 0x02; in _rtl8192ee_read_power_value_fromprom()
1808 pwr2g->ofdm_diff[rf][0] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1810 pwr2g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1811 pwr2g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1812 pwr2g->cck_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1813 pwr2g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1818 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) in _rtl8192ee_read_power_value_fromprom()
1819 pwr5g->index_bw40_base[rf][group] = 0x2A; in _rtl8192ee_read_power_value_fromprom()
1821 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl8192ee_read_power_value_fromprom()
1822 if (i == 0) { in _rtl8192ee_read_power_value_fromprom()
1823 pwr5g->ofdm_diff[rf][0] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1824 pwr5g->bw20_diff[rf][0] = 0x00; in _rtl8192ee_read_power_value_fromprom()
1825 pwr5g->bw80_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1826 pwr5g->bw160_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1828 pwr5g->ofdm_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1829 pwr5g->bw20_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1830 pwr5g->bw40_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1831 pwr5g->bw80_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1832 pwr5g->bw160_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1841 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { in _rtl8192ee_read_power_value_fromprom()
1843 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { in _rtl8192ee_read_power_value_fromprom()
1845 if (pwr2g->index_cck_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1846 pwr2g->index_cck_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1848 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { in _rtl8192ee_read_power_value_fromprom()
1850 if (pwr2g->index_bw40_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1851 pwr2g->index_bw40_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1853 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl8192ee_read_power_value_fromprom()
1854 if (i == 0) { in _rtl8192ee_read_power_value_fromprom()
1855 pwr2g->bw40_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1856 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1857 pwr2g->bw20_diff[rf][i] = 0x02; in _rtl8192ee_read_power_value_fromprom()
1860 & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1862 pwr2g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1865 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1866 pwr2g->ofdm_diff[rf][i] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1869 & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1871 pwr2g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1873 pwr2g->cck_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1876 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1877 pwr2g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1880 & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1882 pwr2g->bw40_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1885 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1886 pwr2g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1889 & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1891 pwr2g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1895 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1896 pwr2g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1899 & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1901 pwr2g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1904 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1905 pwr2g->cck_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1908 & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1910 pwr2g->cck_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1917 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { in _rtl8192ee_read_power_value_fromprom()
1919 if (pwr5g->index_bw40_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1920 pwr5g->index_bw40_base[rf][group] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1923 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl8192ee_read_power_value_fromprom()
1924 if (i == 0) { in _rtl8192ee_read_power_value_fromprom()
1925 pwr5g->bw40_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1927 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1928 pwr5g->bw20_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1930 pwr5g->bw20_diff[rf][0] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1931 & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1933 pwr5g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1936 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1937 pwr5g->ofdm_diff[rf][i] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1939 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1940 & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1942 pwr5g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1946 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1947 pwr5g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1950 & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1952 pwr5g->bw40_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1955 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1956 pwr5g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1959 & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1961 pwr5g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1967 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1968 pwr5g->ofdm_diff[rf][1] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1969 pwr5g->ofdm_diff[rf][2] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1971 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1972 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1976 if (hwinfo[addr] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1977 pwr5g->ofdm_diff[rf][3] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1979 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1983 if (pwr5g->ofdm_diff[rf][i] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1984 pwr5g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1986 pwr5g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1989 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl8192ee_read_power_value_fromprom()
1990 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
1991 pwr5g->bw80_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1993 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0) in _rtl8192ee_read_power_value_fromprom()
1996 pwr5g->bw80_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1999 if (hwinfo[addr] == 0xFF) { in _rtl8192ee_read_power_value_fromprom()
2000 pwr5g->bw160_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
2003 (hwinfo[addr] & 0x0f); in _rtl8192ee_read_power_value_fromprom()
2005 pwr5g->bw160_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
2025 for (rf = 0; rf < MAX_RF_PATH; rf++) { in _rtl92ee_read_txpower_info_from_hwpg()
2026 for (i = 0; i < 14; i++) { in _rtl92ee_read_txpower_info_from_hwpg()
2041 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { in _rtl92ee_read_txpower_info_from_hwpg()
2046 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { in _rtl92ee_read_txpower_info_from_hwpg()
2055 for (i = 0; i < MAX_TX_COUNT; i++) { in _rtl92ee_read_txpower_info_from_hwpg()
2073 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) { in _rtl92ee_read_txpower_info_from_hwpg()
2078 efu->thermalmeter[0] = efu->eeprom_thermalmeter; in _rtl92ee_read_txpower_info_from_hwpg()
2080 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter); in _rtl92ee_read_txpower_info_from_hwpg()
2084 & 0x07; in _rtl92ee_read_txpower_info_from_hwpg()
2085 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF) in _rtl92ee_read_txpower_info_from_hwpg()
2086 efu->eeprom_regulatory = 0; in _rtl92ee_read_txpower_info_from_hwpg()
2088 efu->eeprom_regulatory = 0; in _rtl92ee_read_txpower_info_from_hwpg()
2091 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory); in _rtl92ee_read_txpower_info_from_hwpg()
2112 if (rtlefuse->eeprom_oemid == 0xFF) in _rtl92ee_read_adapter_info()
2113 rtlefuse->eeprom_oemid = 0; in _rtl92ee_read_adapter_info()
2116 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); in _rtl92ee_read_adapter_info()
2128 & 0xE0) >> 5); in _rtl92ee_read_adapter_info()
2129 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF) in _rtl92ee_read_adapter_info()
2130 rtlefuse->board_type = 0; in _rtl92ee_read_adapter_info()
2137 "board_type = 0x%x\n", rtlefuse->board_type); in _rtl92ee_read_adapter_info()
2140 if (hwinfo[EEPROM_XTAL_92E] == 0xFF) in _rtl92ee_read_adapter_info()
2141 rtlefuse->crystalcap = 0x20; in _rtl92ee_read_adapter_info()
2145 rtlefuse->antenna_div_cfg = 0; in _rtl92ee_read_adapter_info()
2150 if (rtlefuse->eeprom_did == 0x818B) { in _rtl92ee_read_adapter_info()
2151 if ((rtlefuse->eeprom_svid == 0x10EC) && in _rtl92ee_read_adapter_info()
2152 (rtlefuse->eeprom_smid == 0x001B)) in _rtl92ee_read_adapter_info()
2175 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); in _rtl92ee_hal_customized_behavior()
2188 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2190 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2193 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", in rtl92ee_read_eeprom_info()
2212 rtlphy->rfpath_rx_enable[0] = true; in rtl92ee_read_eeprom_info()
2219 u8 ret = 0; in _rtl92ee_mrate_idx_to_arfr_id()
2223 ret = 0; in _rtl92ee_mrate_idx_to_arfr_id()
2242 ret = 0; in _rtl92ee_mrate_idx_to_arfr_id()
2259 ? 1 : 0; in rtl92ee_update_hal_rate_mask()
2261 1 : 0; in rtl92ee_update_hal_rate_mask()
2263 1 : 0; in rtl92ee_update_hal_rate_mask()
2264 enum wireless_mode wirelessmode = 0; in rtl92ee_update_hal_rate_mask()
2266 u8 rate_mask[7] = {0}; in rtl92ee_update_hal_rate_mask()
2267 u8 macid = 0; in rtl92ee_update_hal_rate_mask()
2278 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92ee_update_hal_rate_mask()
2280 ratr_bitmap = 0xfff; in rtl92ee_update_hal_rate_mask()
2283 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92ee_update_hal_rate_mask()
2288 if (ratr_bitmap & 0x0000000c) in rtl92ee_update_hal_rate_mask()
2289 ratr_bitmap &= 0x0000000d; in rtl92ee_update_hal_rate_mask()
2291 ratr_bitmap &= 0x0000000f; in rtl92ee_update_hal_rate_mask()
2297 ratr_bitmap &= 0x00000f00; in rtl92ee_update_hal_rate_mask()
2299 ratr_bitmap &= 0x00000ff0; in rtl92ee_update_hal_rate_mask()
2301 ratr_bitmap &= 0x00000ff5; in rtl92ee_update_hal_rate_mask()
2312 ratr_bitmap &= 0x000f0000; in rtl92ee_update_hal_rate_mask()
2314 ratr_bitmap &= 0x000ff000; in rtl92ee_update_hal_rate_mask()
2316 ratr_bitmap &= 0x000ff015; in rtl92ee_update_hal_rate_mask()
2319 ratr_bitmap &= 0x000f0000; in rtl92ee_update_hal_rate_mask()
2321 ratr_bitmap &= 0x000ff000; in rtl92ee_update_hal_rate_mask()
2323 ratr_bitmap &= 0x000ff005; in rtl92ee_update_hal_rate_mask()
2328 ratr_bitmap &= 0x0f8f0000; in rtl92ee_update_hal_rate_mask()
2330 ratr_bitmap &= 0x0ffff000; in rtl92ee_update_hal_rate_mask()
2332 ratr_bitmap &= 0x0ffff015; in rtl92ee_update_hal_rate_mask()
2335 ratr_bitmap &= 0x0f8f0000; in rtl92ee_update_hal_rate_mask()
2337 ratr_bitmap &= 0x0ffff000; in rtl92ee_update_hal_rate_mask()
2339 ratr_bitmap &= 0x0ffff005; in rtl92ee_update_hal_rate_mask()
2345 if (macid == 0) in rtl92ee_update_hal_rate_mask()
2355 ratr_bitmap &= 0x000ff0ff; in rtl92ee_update_hal_rate_mask()
2357 ratr_bitmap &= 0x0f8ff0ff; in rtl92ee_update_hal_rate_mask()
2365 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | in rtl92ee_update_hal_rate_mask()
2367 rate_mask[0] = macid; in rtl92ee_update_hal_rate_mask()
2368 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); in rtl92ee_update_hal_rate_mask()
2370 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); in rtl92ee_update_hal_rate_mask()
2371 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); in rtl92ee_update_hal_rate_mask()
2372 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); in rtl92ee_update_hal_rate_mask()
2373 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); in rtl92ee_update_hal_rate_mask()
2376 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1], in rtl92ee_update_hal_rate_mask()
2380 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92ee_update_hal_rate_mask()
2402 sifs_timer = 0x0a0a; in rtl92ee_update_channel_access_setting()
2404 sifs_timer = 0x0e0e; in rtl92ee_update_channel_access_setting()
2422 u32 entry_id = 0; in rtl92ee_set_key()
2426 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, in rtl92ee_set_key()
2427 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, in rtl92ee_set_key()
2428 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, in rtl92ee_set_key()
2429 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} in rtl92ee_set_key()
2432 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in rtl92ee_set_key()
2436 u8 idx = 0; in rtl92ee_set_key()
2437 u8 cam_offset = 0; in rtl92ee_set_key()
2442 for (idx = 0; idx < clear_number; idx++) { in rtl92ee_set_key()
2447 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92ee_set_key()
2449 rtlpriv->sec.key_len[idx] = 0; in rtl92ee_set_key()
2499 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92ee_set_key()
2548 if (((value & 0xe0) >> 5) == 0x1) in rtl92ee_read_bt_coexist_info_from_hwpg()
2551 rtlpriv->btcoexist.btc_info.btcoexist = 0; in rtl92ee_read_bt_coexist_info_from_hwpg()
2566 /* 0:Low, 1:High, 2:From Efuse. */ in rtl92ee_bt_reg_init()
2568 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ in rtl92ee_bt_reg_init()
2570 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ in rtl92ee_bt_reg_init()
2571 rtlpriv->btcoexist.reg_bt_sco = 0; in rtl92ee_bt_reg_init()
2590 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2606 "receive_config=0x%08X, write_into_reg=%d\n", in rtl92ee_allow_all_destaddr()