Lines Matching +defs:val +defs:data
107 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) argument
108 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) argument
114 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) argument
292 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel()
304 u32 val; in advk_pcie_ltssm_state() local
652 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_rrs, u32 *val) in advk_pcie_check_pio_status()
796 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); in advk_pci_bridge_emul_base_conf_read() local
832 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write() local
840 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write() local
870 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read() local
883 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read() local
1140 int where, int size, u32 *val) in advk_pcie_rd_conf()
1226 int where, int size, u32 val) in advk_pcie_wr_conf()
1296 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, in advk_msi_irq_compose_msi_msg()
1927 u32 val; in advk_pcie_remove() local