Lines Matching +full:0 +full:x68000
31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
363 .cfg_en_adv = 0,
365 .cfg_en_dly = 0,
366 .cfg_tap_adv_3_0 = 0,
368 .cfg_tap_dly_4_0 = 0,
369 .cfg_eq_c_force_3_0 = 0xf,
378 .cfg_tap_adv_3_0 = 0,
380 .cfg_tap_dly_4_0 = 0x10,
381 .cfg_eq_c_force_3_0 = 0xf,
384 .cfg_alos_thr_2_0 = 0,
387 .cfg_en_adv = 0,
389 .cfg_en_dly = 0,
390 .cfg_tap_adv_3_0 = 0,
392 .cfg_tap_dly_4_0 = 0,
393 .cfg_eq_c_force_3_0 = 0xf,
395 .cfg_eq_r_force_3_0 = 0xc,
396 .cfg_alos_thr_2_0 = 0,
403 .tx_pre_div = 0,
404 .fifo_ck_div = 0,
406 .vco_div_mode = 0,
409 .subrate = 0,
410 .com_txcal_en = 0,
411 .com_tx_reserve_msb = (0x26 << 1),
412 .com_tx_reserve_lsb = 0xf0,
413 .cfg_itx_ipcml_base = 0,
414 .tx_reserve_msb = 0xcc,
415 .tx_reserve_lsb = 0xfe,
417 .rxterm = 0,
419 .dfe_tap = 0x1f,
423 .cfg_pi_bw_3_0 = 0,
425 .tx_tap_adv = 0xc,
429 .tx_pre_div = 0,
431 .pre_divsel = 0,
434 .ck_bitwidth = 0,
435 .subrate = 0,
437 .com_tx_reserve_msb = (0x20 << 1),
438 .com_tx_reserve_lsb = 0x40,
439 .cfg_itx_ipcml_base = 0,
440 .tx_reserve_msb = 0x4c,
441 .tx_reserve_lsb = 0x44,
443 .cfg_pi_bw_3_0 = 0,
446 .dfe_tap = 0x1f,
447 .txmargin = 0,
450 .tx_tap_dly = 0,
451 .tx_tap_adv = 0,
455 .tx_pre_div = 0,
457 .pre_divsel = 0,
460 .ck_bitwidth = 0,
461 .subrate = 0,
463 .com_tx_reserve_msb = (0x20 << 1),
464 .com_tx_reserve_lsb = 0,
465 .cfg_itx_ipcml_base = 0,
466 .tx_reserve_msb = 0xe,
467 .tx_reserve_lsb = 0x80,
468 .bw = 0,
469 .rxterm = 0,
471 .dfe_enable = 0,
472 .dfe_tap = 0,
473 .tx_tap_dly = 0,
474 .tx_tap_adv = 0,
478 .tx_pre_div = 0,
479 .fifo_ck_div = 0,
480 .pre_divsel = 0,
486 .com_tx_reserve_msb = (0x26 << 1),
487 .com_tx_reserve_lsb = (0xf << 4),
489 .tx_reserve_msb = 0x8,
490 .tx_reserve_lsb = 0x8a,
491 .bw = 0,
492 .cfg_pi_bw_3_0 = 0,
494 .dfe_enable = 0,
495 .dfe_tap = 0,
496 .tx_tap_dly = 0,
497 .tx_tap_adv = 0,
501 .tx_pre_div = 0,
503 .pre_divsel = 0,
509 .com_tx_reserve_msb = (0x26 << 1),
510 .com_tx_reserve_lsb = 0xf0,
511 .cfg_itx_ipcml_base = 0,
512 .tx_reserve_msb = 0x8,
513 .tx_reserve_lsb = 0xce,
514 .bw = 0,
515 .rxterm = 0,
516 .cfg_pi_bw_3_0 = 0,
517 .dfe_enable = 0,
518 .dfe_tap = 0,
519 .tx_tap_dly = 0,
520 .tx_tap_adv = 0,
526 .cfg_en_adv = 0,
528 .cfg_en_dly = 0,
529 .cfg_tap_adv_3_0 = 0,
531 .cfg_tap_dly_4_0 = 0,
533 .cfg_vga_cp_2_0 = 0,
534 .cfg_eq_res_3_0 = 0xa,
536 .cfg_eq_c_force_3_0 = 0x8,
537 .cfg_alos_thr_3_0 = 0x3,
543 .cfg_tap_adv_3_0 = 0,
545 .cfg_tap_dly_4_0 = 0xc,
546 .cfg_vga_ctrl_3_0 = 0xa,
547 .cfg_vga_cp_2_0 = 0x4,
548 .cfg_eq_res_3_0 = 0xa,
550 .cfg_eq_c_force_3_0 = 0xF,
551 .cfg_alos_thr_3_0 = 0x3,
560 .cfg_vga_ctrl_3_0 = 0xa,
562 .cfg_eq_res_3_0 = 0xa,
564 .cfg_eq_c_force_3_0 = 0xf,
565 .cfg_alos_thr_3_0 = 0x0,
573 .rate = 0x0,
575 .dfe_tap = 0x1f,
576 .pi_bw_gen1 = 0x0,
577 .duty_cycle = 0x2,
582 .rate = 0x1,
583 .dfe_enable = 0,
584 .dfe_tap = 0,
585 .pi_bw_gen1 = 0x5,
586 .duty_cycle = 0x0,
591 .rate = 0x1,
592 .dfe_enable = 0,
593 .dfe_tap = 0,
594 .pi_bw_gen1 = 0x5,
595 .duty_cycle = 0x0,
600 .rate = 0x1,
601 .dfe_enable = 0,
602 .dfe_tap = 0,
603 .pi_bw_gen1 = 0x5,
604 .duty_cycle = 0x0,
609 .rate = 0x2,
610 .dfe_enable = 0,
611 .dfe_tap = 0,
612 .pi_bw_gen1 = 0x7,
613 .duty_cycle = 0x0,
618 .rate = 0x3,
619 .dfe_enable = 0,
620 .dfe_tap = 0,
621 .pi_bw_gen1 = 0x7,
622 .duty_cycle = 0x0,
630 case 10: return 0; in sd25g28_get_iw_setting()
639 return 0; in sd25g28_get_iw_setting()
646 case 10: return 0; in sd10g28_get_iw_setting()
655 return 0; in sd10g28_get_iw_setting()
684 return 0; in sparx5_sd10g25_get_mode_preset()
721 return 0; in sparx5_sd10g28_get_mode_preset()
738 .cfg_vco_start_code_3_0 = 0, in sparx5_sd25g28_get_params()
744 .r_multi_lane_mode = 0, in sparx5_sd25g28_get_params()
747 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
750 .cfg_dmux_pd = 0, in sparx5_sd25g28_get_params()
752 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
755 .cfg_pd_ctle = 0, in sparx5_sd25g28_get_params()
757 .cfg_pmad_ck_pd = 0, in sparx5_sd25g28_get_params()
758 .cfg_pd_clk = 0, in sparx5_sd25g28_get_params()
759 .cfg_pd_cml = 0, in sparx5_sd25g28_get_params()
760 .cfg_pd_driver = 0, in sparx5_sd25g28_get_params()
763 .cfg_dcdr_pd = 0, in sparx5_sd25g28_get_params()
773 .cfg_iscan_en = 0, in sparx5_sd25g28_get_params()
774 .l1_pcs_en_fast_iscan = 0, in sparx5_sd25g28_get_params()
775 .l0_cfg_bw_1_0 = 0, in sparx5_sd25g28_get_params()
776 .cfg_en_dummy = 0, in sparx5_sd25g28_get_params()
785 .cfg_phase_man_4_0 = 0, in sparx5_sd25g28_get_params()
786 .cfg_quad_man_1_0 = 0, in sparx5_sd25g28_get_params()
789 .cfg_txcal_en = 0, in sparx5_sd25g28_get_params()
793 .cfg_pi_steps_1_0 = 0, in sparx5_sd25g28_get_params()
799 .cfg_rx_reserve_7_0 = 0xbf, in sparx5_sd25g28_get_params()
800 .cfg_rx_reserve_15_8 = 0x61, in sparx5_sd25g28_get_params()
802 .cfg_fom_selm = 0, in sparx5_sd25g28_get_params()
803 .cfg_rx_sp_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
804 .cfg_isel_ctle_1_0 = 0, in sparx5_sd25g28_get_params()
817 .r_d_width_ctrl_from_hwt = 0, in sparx5_sd25g28_get_params()
823 .cfg_tx2rx_lp_en = 0, in sparx5_sd25g28_get_params()
824 .cfg_txlb_en = 0, in sparx5_sd25g28_get_params()
825 .cfg_rx2tx_lp_en = 0, in sparx5_sd25g28_get_params()
826 .cfg_rxlb_en = 0, in sparx5_sd25g28_get_params()
854 .r_pcs2pma_phymode_4_0 = 0, in sparx5_sd10g28_get_params()
855 .cfg_lane_id_2_0 = 0, in sparx5_sd10g28_get_params()
858 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
860 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
863 .cfg_pd_ctle = 0, in sparx5_sd10g28_get_params()
865 .cfg_pd_rx_cktree = 0, in sparx5_sd10g28_get_params()
866 .cfg_pd_clk = 0, in sparx5_sd10g28_get_params()
867 .cfg_pd_cml = 0, in sparx5_sd10g28_get_params()
868 .cfg_pd_driver = 0, in sparx5_sd10g28_get_params()
870 .cfg_d_cdr_pd = 0, in sparx5_sd10g28_get_params()
872 .cfg_rxdet_en = 0, in sparx5_sd10g28_get_params()
873 .cfg_rxdet_str = 0, in sparx5_sd10g28_get_params()
874 .r_multi_lane_mode = 0, in sparx5_sd10g28_get_params()
888 .cfg_en_preemph = 0, in sparx5_sd10g28_get_params()
889 .cfg_itx_ippreemp_base_1_0 = 0, in sparx5_sd10g28_get_params()
893 .cfg_dis_2nd_order = 0x1, in sparx5_sd10g28_get_params()
894 .cfg_rx_ssc_lh = 0x0, in sparx5_sd10g28_get_params()
895 .cfg_pi_floop_steps_1_0 = 0x0, in sparx5_sd10g28_get_params()
897 .cfg_pi_ext_dac_15_8 = (0 << 6), in sparx5_sd10g28_get_params()
909 .cfg_pi_steps = 0, in sparx5_sd10g28_get_params()
914 .cfg_itx_ipcml_base_1_0 = 0, in sparx5_sd10g28_get_params()
915 .cfg_ip_pre_base_1_0 = 0, in sparx5_sd10g28_get_params()
919 .r_en_auto_cdr_rstn = 0, in sparx5_sd10g28_get_params()
921 .cfg_pd_osdac_afe = 0, in sparx5_sd10g28_get_params()
922 .cfg_resetb_oscal_afe[0] = 0, in sparx5_sd10g28_get_params()
924 .cfg_center_spreading = 0, in sparx5_sd10g28_get_params()
929 .cfg_tx2rx_lp_en = 0, in sparx5_sd10g28_get_params()
930 .cfg_txlb_en = 0, in sparx5_sd10g28_get_params()
931 .cfg_rx2tx_lp_en = 0, in sparx5_sd10g28_get_params()
932 .cfg_rxlb_en = 0, in sparx5_sd10g28_get_params()
955 spd10g = 0; in sparx5_cmu_apply_cfg()
963 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), in sparx5_cmu_apply_cfg()
973 sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
974 SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
975 SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
976 SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | in sparx5_cmu_apply_cfg()
977 SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_cmu_apply_cfg()
986 sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), in sparx5_cmu_apply_cfg()
991 sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), in sparx5_cmu_apply_cfg()
996 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), in sparx5_cmu_apply_cfg()
1026 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), in sparx5_cmu_apply_cfg()
1033 sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), in sparx5_cmu_apply_cfg()
1049 dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); in sparx5_cmu_apply_cfg()
1052 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), in sparx5_cmu_apply_cfg()
1056 return 0; in sparx5_cmu_apply_cfg()
1066 spd10g = 0; in sparx5_cmu_cfg()
1083 [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
1113 [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
1132 for (i = 0; i < priv->data->consts.cmu_max; i++) { in sparx5_serdes_cmu_power_off()
1136 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_cmu_power_off()
1138 SD_CMU_CFG_SD_CMU_CFG(0)); in sparx5_serdes_cmu_power_off()
1140 sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0), in sparx5_serdes_cmu_power_off()
1142 SD_CMU_CMU_05(0)); in sparx5_serdes_cmu_power_off()
1144 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0), in sparx5_serdes_cmu_power_off()
1146 SD_CMU_CMU_09(0)); in sparx5_serdes_cmu_power_off()
1150 SD_CMU_CMU_06(0)); in sparx5_serdes_cmu_power_off()
1152 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0), in sparx5_serdes_cmu_power_off()
1154 SD_CMU_CMU_09(0)); in sparx5_serdes_cmu_power_off()
1158 SD_CMU_CMU_08(0)); in sparx5_serdes_cmu_power_off()
1166 SD_CMU_CMU_0D(0)); in sparx5_serdes_cmu_power_off()
1170 SD_CMU_CMU_06(0)); in sparx5_serdes_cmu_power_off()
1185 sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd25g28_reset()
1205 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), in sparx5_sd25g28_apply_params()
1252 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), in sparx5_sd25g28_apply_params()
1262 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), in sparx5_sd25g28_apply_params()
1272 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1315 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), in sparx5_sd25g28_apply_params()
1563 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), in sparx5_sd25g28_apply_params()
1573 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd25g28_apply_params()
1578 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), in sparx5_sd25g28_apply_params()
1592 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), in sparx5_sd25g28_apply_params()
1601 dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1608 if (value != 0x1) { in sparx5_sd25g28_apply_params()
1609 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); in sparx5_sd25g28_apply_params()
1612 sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), in sparx5_sd25g28_apply_params()
1617 sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1622 sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd25g28_apply_params()
1627 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), in sparx5_sd25g28_apply_params()
1638 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), in sparx5_sd25g28_apply_params()
1643 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), in sparx5_sd25g28_apply_params()
1648 return 0; in sparx5_sd25g28_apply_params()
1660 sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_sd10g28_reset()
1679 return 0; in sparx5_sd10g28_apply_params()
1696 sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1697 SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) | in sparx5_sd10g28_apply_params()
1698 SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1699 SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) | in sparx5_sd10g28_apply_params()
1700 SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0), in sparx5_sd10g28_apply_params()
1709 sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1710 SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1711 SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) | in sparx5_sd10g28_apply_params()
1712 SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1720 sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1), in sparx5_sd10g28_apply_params()
1725 sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1726 SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) | in sparx5_sd10g28_apply_params()
1727 SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1), in sparx5_sd10g28_apply_params()
2025 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
2061 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), in sparx5_sd10g28_apply_params()
2096 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); in sparx5_sd10g28_apply_params()
2100 sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2105 sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), in sparx5_sd10g28_apply_params()
2110 return 0; in sparx5_sd10g28_apply_params()
2119 .txinvert = 0, in sparx5_sd25g28_config()
2121 .com_pll_reserve = 0xf, in sparx5_sd25g28_config()
2142 .txinvert = 0, in sparx5_sd10g28_config()
2175 sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_power_save()
2177 SD_LANE_25G_SD_LANE_CFG(0)); in sparx5_serdes_power_save()
2182 sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0)); in sparx5_serdes_power_save()
2187 SD25G_LANE_LANE_04(0)); in sparx5_serdes_power_save()
2193 sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), in sparx5_serdes_power_save()
2195 SD_LANE_SD_LANE_CFG(0)); in sparx5_serdes_power_save()
2200 SD_LANE_QUIET_MODE_6G(0)); in sparx5_serdes_power_save()
2205 SD10G_LANE_LANE_06(0)); in sparx5_serdes_power_save()
2207 return 0; in sparx5_serdes_power_save()
2216 return 0; in sparx5_serdes_clock_config()
2220 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
2227 return 0; in sparx5_serdes_clock_config()
2259 if (serdesmode < 0) { in sparx5_serdes_config()
2310 return 0; in sparx5_serdes_set_mode()
2325 return 0; in sparx5_serdes_set_media()
2343 return 0; in sparx5_serdes_set_speed()
2371 if (macro->speed == 0) in sparx5_serdes_validate()
2401 return 0; in sparx5_serdes_validate()
2459 return 0; in sparx5_phy_create()
2463 { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */
2464 { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */
2465 { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */
2466 { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */
2467 { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */
2468 { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */
2469 { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */
2470 { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */
2471 { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */
2472 { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */
2473 { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */
2474 { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */
2475 { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */
2476 { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */
2477 { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */
2478 { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */
2479 { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */
2480 { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */
2481 { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */
2482 { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */
2483 { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */
2484 { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */
2485 { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */
2486 { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */
2487 { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */
2488 { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */
2489 { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */
2490 { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */
2491 { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */
2492 { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */
2493 { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */
2494 { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */
2495 { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */
2496 { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */
2497 { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */
2498 { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */
2499 { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */
2500 { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */
2501 { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */
2502 { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */
2503 { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */
2504 { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */
2505 { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */
2506 { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */
2507 { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */
2508 { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */
2509 { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */
2510 { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */
2511 { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */
2512 { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */
2513 { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */
2514 { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */
2515 { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */
2516 { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */
2517 { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */
2518 { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */
2519 { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */
2520 { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */
2521 { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */
2522 { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */
2523 { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */
2524 { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */
2525 { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */
2526 { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */
2527 { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */
2528 { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */
2529 { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */
2530 { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */
2531 { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */
2532 { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */
2533 { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */
2534 { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */
2535 { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */
2536 { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */
2537 { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */
2538 { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */
2539 { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */
2540 { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */
2541 { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */
2542 { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */
2543 { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */
2544 { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */
2545 { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */
2546 { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */
2547 { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */
2548 { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */
2549 { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */
2550 { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */
2551 { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */
2552 { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */
2553 { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */
2554 { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */
2555 { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */
2556 { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
2560 { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */
2561 { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */
2562 { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */
2563 { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */
2564 { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */
2565 { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */
2566 { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */
2567 { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */
2568 { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */
2569 { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */
2570 { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */
2571 { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */
2572 { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */
2573 { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */
2574 { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */
2575 { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */
2576 { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */
2577 { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */
2578 { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */
2579 { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */
2580 { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */
2581 { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */
2582 { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */
2583 { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */
2584 { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */
2585 { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */
2586 { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */
2587 { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */
2588 { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */
2589 { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */
2590 { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */
2591 { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */
2635 sidx = args->args[0]; in sparx5_serdes_xlate()
2638 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { in sparx5_serdes_xlate()
2685 if (clock == 0) { in sparx5_serdes_probe()
2691 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); in sparx5_serdes_probe()
2702 for (idx = 0; idx < priv->data->iomap_size; idx++) { in sparx5_serdes_probe()
2708 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { in sparx5_serdes_probe()