54 	u32 val = readl(reg) & ~mask;  in airoha_phy_clear_bits()  local
61 	u32 val = readl(reg) | mask;  in airoha_phy_set_bits()  local
66 static void airoha_phy_update_bits(void __iomem *reg, u32 mask, u32 val)  in airoha_phy_update_bits()
75 #define airoha_phy_update_field(reg, mask, val)					\  argument
87 #define airoha_phy_csr_2l_update_field(pcie_phy, reg, mask, val)		\  argument
97 #define airoha_phy_pma0_update_field(pcie_phy, reg, mask, val)			\  argument
99 #define airoha_phy_pma1_update_field(pcie_phy, reg, mask, val)			\  argument
108 	u32 pr_idac, val, cdr_pr_idac_tmp = 0;  in airoha_phy_init_lane0_rx_fw_pre_calib()  local
214 		u32 val;  in airoha_phy_init_lane0_rx_fw_pre_calib()  local
269 	u32 pr_idac, val, cdr_pr_idac_tmp = 0;  in airoha_phy_init_lane1_rx_fw_pre_calib()  local
374 		u32 val;  in airoha_phy_init_lane1_rx_fw_pre_calib()  local
1113 	u32 val;  in airoha_pcie_phy_init()  local
1219 	struct phy_provider *provider;  in airoha_pcie_phy_probe()  local