Lines Matching full:edp
76 int (*com_power_on)(const struct qcom_edp *edp);
77 int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
78 int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
79 int (*com_configure_pll)(const struct qcom_edp *edp);
80 int (*com_configure_ssc)(const struct qcom_edp *edp);
96 void __iomem *edp; member
213 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_init() local
217 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
221 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_init()
225 memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); in qcom_edp_phy_init()
229 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
231 ret = edp->cfg->ver_ops->com_bias_en_clkbuflr(edp); in qcom_edp_phy_init()
235 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
241 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
248 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) in qcom_edp_phy_init()
251 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
254 writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); in qcom_edp_phy_init()
258 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK); in qcom_edp_phy_init()
265 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
270 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) in qcom_edp_set_voltages() argument
272 const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg; in qcom_edp_set_voltages()
283 if (edp->is_edp) in qcom_edp_set_voltages()
302 ldo_config = edp->is_edp ? 0x0 : 0x1; in qcom_edp_set_voltages()
304 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
305 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
306 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
308 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
309 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
310 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
318 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_configure() local
321 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_edp_phy_configure()
324 ret = qcom_edp_set_voltages(edp, dp_opts); in qcom_edp_phy_configure()
329 static int qcom_edp_configure_ssc(const struct qcom_edp *edp) in qcom_edp_configure_ssc() argument
331 return edp->cfg->ver_ops->com_configure_ssc(edp); in qcom_edp_configure_ssc()
334 static int qcom_edp_configure_pll(const struct qcom_edp *edp) in qcom_edp_configure_pll() argument
336 return edp->cfg->ver_ops->com_configure_pll(edp); in qcom_edp_configure_pll()
339 static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq) in qcom_edp_set_vco_div() argument
341 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_set_vco_div()
370 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); in qcom_edp_set_vco_div()
375 static int qcom_edp_phy_power_on_v4(const struct qcom_edp *edp) in qcom_edp_phy_power_on_v4() argument
382 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v4()
383 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v4()
385 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, in qcom_edp_phy_power_on_v4()
389 static int qcom_edp_phy_com_resetsm_cntrl_v4(const struct qcom_edp *edp) in qcom_edp_phy_com_resetsm_cntrl_v4() argument
393 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v4()
395 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v4()
399 static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) in qcom_edp_com_bias_en_clkbuflr_v4() argument
402 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v4()
407 static int qcom_edp_com_configure_ssc_v4(const struct qcom_edp *edp) in qcom_edp_com_configure_ssc_v4() argument
409 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v4()
431 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v4()
432 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v4()
433 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v4()
434 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v4()
435 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v4()
436 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v4()
441 static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp) in qcom_edp_com_configure_pll_v4() argument
443 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v4()
493 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v4()
494 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v4()
495 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v4()
496 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v4()
497 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v4()
498 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v4()
499 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); in qcom_edp_com_configure_pll_v4()
500 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v4()
501 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v4()
502 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
503 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
504 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v4()
505 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v4()
506 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v4()
507 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v4()
508 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v4()
509 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); in qcom_edp_com_configure_pll_v4()
510 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v4()
511 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v4()
512 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v4()
513 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v4()
514 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v4()
516 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); in qcom_edp_com_configure_pll_v4()
517 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); in qcom_edp_com_configure_pll_v4()
518 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v4()
519 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_configure_pll_v4()
520 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v4()
521 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v4()
522 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v4()
560 static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp) in qcom_edp_phy_power_on_v6() argument
567 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v6()
568 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v6()
570 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS, in qcom_edp_phy_power_on_v6()
574 static int qcom_edp_phy_com_resetsm_cntrl_v6(const struct qcom_edp *edp) in qcom_edp_phy_com_resetsm_cntrl_v6() argument
578 writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v6()
580 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v6()
584 static int qcom_edp_com_bias_en_clkbuflr_v6(const struct qcom_edp *edp) in qcom_edp_com_bias_en_clkbuflr_v6() argument
587 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v6()
592 static int qcom_edp_com_configure_ssc_v6(const struct qcom_edp *edp) in qcom_edp_com_configure_ssc_v6() argument
594 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v6()
616 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v6()
617 writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v6()
618 writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v6()
619 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v6()
620 writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v6()
621 writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v6()
626 static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp) in qcom_edp_com_configure_pll_v6() argument
628 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v6()
688 writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v6()
689 writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v6()
690 writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v6()
691 writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v6()
692 writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v6()
693 writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v6()
694 writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1); in qcom_edp_com_configure_pll_v6()
695 writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v6()
696 writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v6()
697 writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
698 writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
699 writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v6()
700 writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v6()
701 writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v6()
702 writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v6()
703 writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v6()
704 writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1); in qcom_edp_com_configure_pll_v6()
705 writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v6()
706 writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v6()
707 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v6()
708 writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v6()
709 writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v6()
711 writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER); in qcom_edp_com_configure_pll_v6()
712 writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0); in qcom_edp_com_configure_pll_v6()
713 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v6()
714 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_configure_pll_v6()
715 writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v6()
716 writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v6()
717 writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v6()
719 writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0); in qcom_edp_com_configure_pll_v6()
720 writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0); in qcom_edp_com_configure_pll_v6()
741 const struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_power_on() local
749 ret = edp->cfg->ver_ops->com_power_on(edp); in qcom_edp_phy_power_on()
753 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) in qcom_edp_phy_power_on()
756 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
757 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_phy_power_on()
758 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
759 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
761 if (edp->dp_opts.ssc) { in qcom_edp_phy_power_on()
762 ret = qcom_edp_configure_ssc(edp); in qcom_edp_phy_power_on()
767 ret = qcom_edp_configure_pll(edp); in qcom_edp_phy_power_on()
772 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); in qcom_edp_phy_power_on()
773 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); in qcom_edp_phy_power_on()
776 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
777 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
778 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
779 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
780 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
783 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
784 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
785 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
786 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
787 writel(0x04, edp->tx1 + TXn_TX_BAND); in qcom_edp_phy_power_on()
789 ret = qcom_edp_set_vco_div(edp, &pixel_freq); in qcom_edp_phy_power_on()
793 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
794 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
795 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
796 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
798 ret = edp->cfg->ver_ops->com_resetsm_cntrl(edp); in qcom_edp_phy_power_on()
802 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
803 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
804 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
805 writel(0x00, edp->tx0 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
806 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
807 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
808 writel(0x00, edp->tx1 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
809 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
810 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
811 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
812 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
813 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
814 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
816 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
817 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
818 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
819 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
821 if (edp->dp_opts.lanes == 1) { in qcom_edp_phy_power_on()
827 } else if (edp->dp_opts.lanes == 2) { in qcom_edp_phy_power_on()
841 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
842 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
843 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
844 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
845 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
847 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
850 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
852 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, in qcom_edp_phy_power_on()
857 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); in qcom_edp_phy_power_on()
858 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); in qcom_edp_phy_power_on()
865 const struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_power_off() local
867 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_off()
874 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_set_mode() local
879 edp->is_edp = submode == PHY_SUBMODE_EDP; in qcom_edp_phy_set_mode()
886 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_exit() local
888 clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_exit()
889 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_exit()
911 * | | (EDP PLL/VCO) | |
950 * for EDP pixel clock
970 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_pixel_hw); in qcom_edp_dp_pixel_clk_recalc_rate() local
971 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_pixel_clk_recalc_rate()
1010 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_link_hw); in qcom_edp_dp_link_clk_recalc_rate() local
1011 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_link_clk_recalc_rate()
1030 static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) in qcom_edp_clks_register() argument
1037 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); in qcom_edp_clks_register()
1042 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1045 edp->dp_link_hw.init = &init; in qcom_edp_clks_register()
1046 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); in qcom_edp_clks_register()
1050 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1053 edp->dp_pixel_hw.init = &init; in qcom_edp_clks_register()
1054 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); in qcom_edp_clks_register()
1058 data->hws[0] = &edp->dp_link_hw; in qcom_edp_clks_register()
1059 data->hws[1] = &edp->dp_pixel_hw; in qcom_edp_clks_register()
1061 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); in qcom_edp_clks_register()
1068 struct qcom_edp *edp; in qcom_edp_phy_probe() local
1071 edp = devm_kzalloc(dev, sizeof(*edp), GFP_KERNEL); in qcom_edp_phy_probe()
1072 if (!edp) in qcom_edp_phy_probe()
1075 edp->dev = dev; in qcom_edp_phy_probe()
1076 edp->cfg = of_device_get_match_data(&pdev->dev); in qcom_edp_phy_probe()
1077 edp->is_edp = edp->cfg->is_edp; in qcom_edp_phy_probe()
1079 edp->edp = devm_platform_ioremap_resource(pdev, 0); in qcom_edp_phy_probe()
1080 if (IS_ERR(edp->edp)) in qcom_edp_phy_probe()
1081 return PTR_ERR(edp->edp); in qcom_edp_phy_probe()
1083 edp->tx0 = devm_platform_ioremap_resource(pdev, 1); in qcom_edp_phy_probe()
1084 if (IS_ERR(edp->tx0)) in qcom_edp_phy_probe()
1085 return PTR_ERR(edp->tx0); in qcom_edp_phy_probe()
1087 edp->tx1 = devm_platform_ioremap_resource(pdev, 2); in qcom_edp_phy_probe()
1088 if (IS_ERR(edp->tx1)) in qcom_edp_phy_probe()
1089 return PTR_ERR(edp->tx1); in qcom_edp_phy_probe()
1091 edp->pll = devm_platform_ioremap_resource(pdev, 3); in qcom_edp_phy_probe()
1092 if (IS_ERR(edp->pll)) in qcom_edp_phy_probe()
1093 return PTR_ERR(edp->pll); in qcom_edp_phy_probe()
1095 edp->clks[0].id = "aux"; in qcom_edp_phy_probe()
1096 edp->clks[1].id = "cfg_ahb"; in qcom_edp_phy_probe()
1097 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_probe()
1101 edp->supplies[0].supply = "vdda-phy"; in qcom_edp_phy_probe()
1102 edp->supplies[1].supply = "vdda-pll"; in qcom_edp_phy_probe()
1103 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_probe()
1107 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ in qcom_edp_phy_probe()
1109 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); in qcom_edp_phy_probe()
1113 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ in qcom_edp_phy_probe()
1115 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); in qcom_edp_phy_probe()
1119 ret = qcom_edp_clks_register(edp, pdev->dev.of_node); in qcom_edp_phy_probe()
1123 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops); in qcom_edp_phy_probe()
1124 if (IS_ERR(edp->phy)) { in qcom_edp_phy_probe()
1126 return PTR_ERR(edp->phy); in qcom_edp_phy_probe()
1129 phy_set_drvdata(edp->phy, edp); in qcom_edp_phy_probe()
1136 { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
1137 { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
1138 { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
1140 { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
1149 .name = "qcom-edp-phy",
1157 MODULE_DESCRIPTION("Qualcomm eDP QMP PHY driver");