Lines Matching +full:x1e80100 +full:- +full:gcc
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
43 /* set of registers with offsets different per-PHY */
2935 /* struct qmp_phy_cfg - per-PHY initialization config */
2941 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
3047 "vdda-phy", "vdda-pll",
3051 "vdda-phy", "vdda-pll", "vdda-qref",
4161 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
4162 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_init_port_b()
4165 serdes = qmp->port_b + offs->serdes; in qmp_pcie_init_port_b()
4166 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
4167 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
4168 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
4169 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
4170 pcs = qmp->port_b + offs->pcs; in qmp_pcie_init_port_b()
4171 pcs_misc = qmp->port_b + offs->pcs_misc; in qmp_pcie_init_port_b()
4172 ln_shrd = qmp->port_b + offs->ln_shrd; in qmp_pcie_init_port_b()
4174 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_port_b()
4175 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); in qmp_pcie_init_port_b()
4177 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_port_b()
4178 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_port_b()
4180 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_port_b()
4181 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_port_b()
4183 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_port_b()
4184 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_port_b()
4186 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_port_b()
4191 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
4192 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
4193 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers()
4194 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
4195 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
4196 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
4197 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers()
4198 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
4199 void __iomem *pcs_lane1 = qmp->pcs_lane1; in qmp_pcie_init_registers()
4200 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
4205 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_registers()
4211 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); in qmp_pcie_init_registers()
4212 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); in qmp_pcie_init_registers()
4214 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_registers()
4215 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_registers()
4217 if (cfg->lanes >= 2) { in qmp_pcie_init_registers()
4218 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_registers()
4219 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_registers()
4222 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_registers()
4223 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_registers()
4224 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); in qmp_pcie_init_registers()
4226 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
4227 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, in qmp_pcie_init_registers()
4228 cfg->serdes_4ln_num); in qmp_pcie_init_registers()
4232 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_registers()
4238 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
4241 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4243 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
4247 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4249 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
4253 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
4255 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
4261 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4263 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
4267 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
4274 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4276 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4284 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
4286 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
4288 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
4290 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
4298 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
4300 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on()
4305 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_on()
4306 cfg->pwrdn_ctrl); in qmp_pcie_power_on()
4308 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
4309 mode_tbls = cfg->tbls_rc; in qmp_pcie_power_on()
4311 mode_tbls = cfg->tbls_ep; in qmp_pcie_power_on()
4313 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
4316 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4320 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
4322 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
4327 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
4329 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
4330 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_pcie_power_on()
4332 if (!cfg->skip_start_delay) in qmp_pcie_power_on()
4335 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
4336 mask = cfg->phy_status; in qmp_pcie_power_on()
4340 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
4347 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4355 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
4357 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
4360 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
4362 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
4363 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
4367 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
4368 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
4406 qmp->mode = submode; in qmp_pcie_set_mode()
4409 dev_err(&phy->dev, "Unsupported submode %d\n", submode); in qmp_pcie_set_mode()
4410 return -EINVAL; in qmp_pcie_set_mode()
4425 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
4426 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
4427 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
4430 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
4431 if (!qmp->vregs) in qmp_pcie_vreg_init()
4432 return -ENOMEM; in qmp_pcie_vreg_init()
4435 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
4437 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
4442 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
4443 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
4447 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
4448 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
4449 if (!qmp->resets) in qmp_pcie_reset_init()
4450 return -ENOMEM; in qmp_pcie_reset_init()
4452 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
4453 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
4455 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
4459 if (cfg->has_nocsr_reset) { in qmp_pcie_reset_init()
4460 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
4461 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
4462 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
4463 "failed to get no-csr reset\n"); in qmp_pcie_reset_init()
4471 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
4475 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
4476 if (!qmp->clks) in qmp_pcie_clk_init()
4477 return -ENOMEM; in qmp_pcie_clk_init()
4480 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
4482 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
4493 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4494 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4496 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4500 * +---------------+
4501 * | PHY block |<<---------------------------------------+
4503 * | +-------+ | +-----+ |
4504 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4505 * clk | +-------+ | +-----+
4506 * +---------------+
4510 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
4514 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); in phy_pipe_clk_register()
4516 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
4523 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
4526 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
4527 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
4529 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
4531 fixed->hw.init = &init; in phy_pipe_clk_register()
4533 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
4539 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4540 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4542 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4546 * +---------------+
4547 * | PHY block |<<---------------------------------------------+
4549 * | +-------+ | +-----+ |
4550 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4551 * clk | +-------+ | +-----+
4552 * +---------------+
4556 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; in phy_aux_clk_register()
4560 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); in phy_aux_clk_register()
4565 fixed->fixed_rate = qmp->cfg->aux_clock_rate; in phy_aux_clk_register()
4566 fixed->hw.init = &init; in phy_aux_clk_register()
4568 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_aux_clk_register()
4576 if (!clkspec->args_count) in qmp_pcie_clk_hw_get()
4577 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4579 switch (clkspec->args[0]) { in qmp_pcie_clk_hw_get()
4581 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4583 return &qmp->aux_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4586 return ERR_PTR(-EINVAL); in qmp_pcie_clk_hw_get()
4597 if (qmp->cfg->aux_clock_rate) { in qmp_pcie_register_clocks()
4606 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); in qmp_pcie_register_clocks()
4615 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in qmp_pcie_register_clocks()
4620 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
4621 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
4622 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
4625 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
4626 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
4627 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
4631 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_parse_dt_legacy()
4632 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_parse_dt_legacy()
4633 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_parse_dt_legacy()
4635 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
4636 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
4637 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
4639 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4640 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
4642 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
4643 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
4644 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
4646 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
4647 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
4648 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
4650 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt_legacy()
4651 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4652 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
4653 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
4655 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
4656 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
4657 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
4659 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
4661 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4664 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
4665 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4666 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
4668 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4669 if (cfg->tbls.pcs_misc || in qmp_pcie_parse_dt_legacy()
4670 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || in qmp_pcie_parse_dt_legacy()
4671 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4672 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
4680 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) in qmp_pcie_parse_dt_legacy()
4681 qmp->pcs_lane1 = qmp->pcs_misc + in qmp_pcie_parse_dt_legacy()
4682 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); in qmp_pcie_parse_dt_legacy()
4690 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
4691 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
4692 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
4703 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
4704 "qcom,4ln-config-sel", in qmp_pcie_get_4ln_config()
4708 if (ret == -ENOENT) in qmp_pcie_get_4ln_config()
4711 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
4717 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
4721 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
4723 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
4730 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
4731 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
4732 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_parse_dt()
4733 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
4738 return -EINVAL; in qmp_pcie_parse_dt()
4748 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
4749 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
4750 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
4751 qmp->pcs_lane1 = base + offs->pcs_lane1; in qmp_pcie_parse_dt()
4752 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
4753 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
4755 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt()
4756 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
4757 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
4760 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
4761 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
4762 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
4763 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
4766 qmp->txz = base + offs->txz; in qmp_pcie_parse_dt()
4767 qmp->rxz = base + offs->rxz; in qmp_pcie_parse_dt()
4769 if (cfg->tbls.ln_shrd) in qmp_pcie_parse_dt()
4770 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
4772 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
4773 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
4774 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
4776 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
4780 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
4789 struct device *dev = &pdev->dev; in qmp_pcie_probe()
4797 return -ENOMEM; in qmp_pcie_probe()
4799 qmp->dev = dev; in qmp_pcie_probe()
4801 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
4802 if (!qmp->cfg) in qmp_pcie_probe()
4803 return -EINVAL; in qmp_pcie_probe()
4805 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
4806 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
4821 np = of_get_next_available_child(dev->of_node, NULL); in qmp_pcie_probe()
4825 np = of_node_get(dev->of_node); in qmp_pcie_probe()
4835 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
4837 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
4838 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
4839 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
4844 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
4859 .compatible = "qcom,ipq6018-qmp-pcie-phy",
4862 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
4865 .compatible = "qcom,ipq8074-qmp-pcie-phy",
4868 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
4871 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
4874 .compatible = "qcom,msm8998-qmp-pcie-phy",
4877 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
4880 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
4883 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
4886 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
4889 .compatible = "qcom,sc8180x-qmp-pcie-phy",
4892 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
4895 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
4898 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
4901 .compatible = "qcom,sdm845-qhp-pcie-phy",
4904 .compatible = "qcom,sdm845-qmp-pcie-phy",
4907 .compatible = "qcom,sdx55-qmp-pcie-phy",
4910 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
4913 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
4916 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
4919 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
4922 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
4925 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
4928 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
4931 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
4934 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
4937 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
4940 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
4943 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
4946 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
4949 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
4952 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
4955 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
4958 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
4961 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
4971 .name = "qcom-qmp-pcie-phy",