30  * Lane Registers
163 /* Lane 0/1/2/3 offset */
174 	/* Lane 0/1/2/3 Register */
184  * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198  * struct xpsgtr_phy - representation of a lane
200  * @instance: instance of the protocol type (such as the lane within a
202  * @lane: lane number
203  * @protocol: protocol in which the lane operates
211 	u8 lane;  member
294 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_read_phy()
303 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_write_phy()
312 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_clr_set_phy()
395 			"lane %u (protocol %u, instance %u): PLL lock timeout\n",  in xpsgtr_wait_pll_lock()
396 			gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);  in xpsgtr_wait_pll_lock()
410 	xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
413 	/* Enable lane clock sharing, if required */  in xpsgtr_configure_pll()
414 	if (gtr_phy->refclk == gtr_phy->lane)  in xpsgtr_configure_pll()
415 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
418 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
451 /* Configure the lane protocol. */
457 	switch (gtr_phy->lane) {  in xpsgtr_lane_set_protocol()
473 		/* We already checked 0 <= lane <= 3 */  in xpsgtr_lane_set_protocol()
505 	writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);  in xpsgtr_phy_init_sata()
512 	u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);  in xpsgtr_phy_init_sgmii()
513 	u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);  in xpsgtr_phy_init_sgmii()
554 	 * shutdown during suspend or when gt lane is changed from current one)  in xpsgtr_phy_init_required()
584 	 * we need to configure any lane ICM_CFG to valid protocol. This  in xpsgtr_phy_tx_term_fix()
658 	 * Configure the PLL, the lane protocol, and perform protocol-specific  in xpsgtr_phy_init()
690 	/* Ensure that disable clock only, which configure for lane */  in xpsgtr_phy_exit()
731 /* Set the lane protocol and instance based on the PHY type and instance number. */
771  * "instance" represents one controller for a lane. For PCIe and DP, the
772  * "instance" is the logical lane in the link. For SATA, USB, and SGMII,
780 	{ 0, 0, 0, 1, 0 }, /* Lane 0 */
781 	{ 1, 1, 0, 0, 1 }, /* Lane 1 */
782 	{ 2, 0, 0, 1, 2 }, /* Lane 2 */
783 	{ 3, 1, 1, 0, 3 }, /* Lane 3 */
805 	 * Get the PHY parameters from the OF arguments and derive the lane  in xpsgtr_xlate()
810 		dev_err(dev, "Invalid lane number %u\n", phy_lane);  in xpsgtr_xlate()
835 	 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type  in xpsgtr_xlate()
836 	 * is allowed to operate on the lane.  in xpsgtr_xlate()
861 	seq_printf(seq, "Lane:            %u\n", gtr_phy->lane);  in xpsgtr_status_read()
1016 		gtr_phy->lane = port;  in xpsgtr_probe()