Lines Matching +full:mux +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0
24 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/platform_data/x86/pwm-lpss.h>
31 #include "pinctrl-intel.h"
91 * 0 0 0 -
126 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
127 #define padgroup_offset(g, p) ((p) - (g)->base)
131 __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
136 __gi < community->ngpps && (grp = &community->gpps[__gi]); \
145 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
153 if (pin >= community->pin_base && in intel_get_community()
154 pin < community->pin_base + community->npins) in intel_get_community()
158 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); in intel_get_community()
170 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) in intel_community_get_padgroup()
189 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; in intel_get_padcfg()
194 return community->pad_regs + reg + padno * nregs * 4; in intel_get_padcfg()
207 if (!community->padown_offset) in intel_pad_owned_by_host()
216 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; in intel_pad_owned_by_host()
217 padown = community->regs + offset; in intel_pad_owned_by_host()
232 if (!community->hostown_offset) in intel_pad_acpi_mode()
240 offset = community->hostown_offset + padgrp->reg_num * 4; in intel_pad_acpi_mode()
241 hostown = community->regs + offset; in intel_pad_acpi_mode()
247 * enum - Locking variants of the pad configuration
249 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
250 * @PAD_LOCKED_TX: pad configuration TX state is locked
251 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
253 * Locking is considered as read-only mode for corresponding registers and
254 * their respective fields. That said, TX state bit is locked separately from
275 if (!community->padcfglock_offset) in intel_pad_locked()
287 * either fully or partially locked. in intel_pad_locked()
289 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; in intel_pad_locked()
290 value = readl(community->regs + offset); in intel_pad_locked()
294 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; in intel_pad_locked()
295 value = readl(community->regs + offset); in intel_pad_locked()
316 return pctrl->soc->ngroups; in intel_get_groups_count()
324 return pctrl->soc->groups[group].grp.name; in intel_get_group_name()
333 *pins = pctrl->soc->groups[group].grp.pins; in intel_get_group_pins()
334 *npins = pctrl->soc->groups[group].grp.npins; in intel_get_group_pins()
345 int locked; in intel_pin_dbg_show() local
369 locked = intel_pad_locked(pctrl, pin); in intel_pin_dbg_show()
372 if (locked || acpi) { in intel_pin_dbg_show()
374 if (locked) in intel_pin_dbg_show()
375 seq_puts(s, "LOCKED"); in intel_pin_dbg_show()
376 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) in intel_pin_dbg_show()
378 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) in intel_pin_dbg_show()
381 if (locked && acpi) in intel_pin_dbg_show()
401 return pctrl->soc->nfunctions; in intel_get_functions_count()
409 return pctrl->soc->functions[function].func.name; in intel_get_function_name()
418 *groups = pctrl->soc->functions[function].func.groups; in intel_get_function_groups()
419 *ngroups = pctrl->soc->functions[function].func.ngroups; in intel_get_function_groups()
428 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; in intel_pinmux_set_mux()
431 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_pinmux_set_mux()
435 * before we can enable the mux for this group. in intel_pinmux_set_mux()
437 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
438 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) in intel_pinmux_set_mux()
439 return -EBUSY; in intel_pinmux_set_mux()
442 /* Now enable the mux setting for each pin in the group */ in intel_pinmux_set_mux()
443 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
447 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); in intel_pinmux_set_mux()
452 if (grp->modes) in intel_pinmux_set_mux()
453 pmode = grp->modes[i]; in intel_pinmux_set_mux()
455 pmode = grp->mode; in intel_pinmux_set_mux()
465 * enum - Possible pad physical connections
490 return -ENOTSUPP; in __intel_gpio_get_direction()
548 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_request_enable()
551 return -EBUSY; in intel_gpio_request_enable()
580 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_set_direction()
609 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_config_get_pull()
617 return -EINVAL; in intel_config_get_pull()
622 return -EINVAL; in intel_config_get_pull()
648 return -EINVAL; in intel_config_get_pull()
652 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
653 return -EINVAL; in intel_config_get_pull()
657 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
658 return -EINVAL; in intel_config_get_pull()
676 return -EINVAL; in intel_config_get_pull()
690 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_config_get_high_impedance()
694 return -EINVAL; in intel_config_get_high_impedance()
708 return -ENOTSUPP; in intel_config_get_debounce()
710 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_config_get_debounce()
714 return -EINVAL; in intel_config_get_debounce()
731 return -ENOTSUPP; in intel_config_get()
755 return -ENOTSUPP; in intel_config_get()
793 return -EINVAL; in intel_config_set_pull()
814 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_set_pull()
815 return -EINVAL; in intel_config_set_pull()
819 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_set_pull()
820 return -EINVAL; in intel_config_set_pull()
824 return -EINVAL; in intel_config_set_pull()
831 return -EINVAL; in intel_config_set_pull()
836 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_config_set_pull()
853 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_set_high_impedance()
870 return -EINVAL; in intel_config_set_debounce()
877 return -ENOTSUPP; in intel_config_set_debounce()
881 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_config_set_debounce()
910 return -ENOTSUPP; in intel_config_set()
934 return -ENOTSUPP; in intel_config_set()
955 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
976 if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) { in intel_gpio_to_pin()
982 return grp->base + offset - grp->gpio_base; in intel_gpio_to_pin()
986 return -EINVAL; in intel_gpio_to_pin()
990 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
1005 return -EINVAL; in intel_pin_to_gpio()
1009 return -EINVAL; in intel_pin_to_gpio()
1011 return pin - padgrp->base + padgrp->gpio_base; in intel_pin_to_gpio()
1023 return -EINVAL; in intel_gpio_get()
1027 return -EINVAL; in intel_gpio_get()
1052 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_set()
1071 return -EINVAL; in intel_gpio_get_direction()
1075 return -EINVAL; in intel_gpio_get_direction()
1077 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) in intel_gpio_get_direction()
1081 return -EINVAL; in intel_gpio_get_direction()
1126 gpp = padgrp->reg_num; in intel_gpio_irq_ack()
1129 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_ack()
1131 guard(raw_spinlock)(&pctrl->lock); in intel_gpio_irq_ack()
1150 gpp = padgrp->reg_num; in intel_gpio_irq_mask_unmask()
1153 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1154 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1156 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_irq_mask_unmask()
1198 return -EINVAL; in intel_gpio_irq_type()
1206 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); in intel_gpio_irq_type()
1207 return -EPERM; in intel_gpio_irq_type()
1227 guard(raw_spinlock_irqsave)(&pctrl->lock); in intel_gpio_irq_type()
1253 enable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1255 disable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1257 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); in intel_gpio_irq_wake()
1262 .name = "intel-gpio",
1281 struct gpio_chip *gc = &pctrl->chip; in intel_gpio_irq()
1286 gpp = padgrp->reg_num; in intel_gpio_irq()
1288 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq()
1289 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq()
1291 scoped_guard(raw_spinlock, &pctrl->lock) { in intel_gpio_irq()
1299 for_each_set_bit(gpp_offset, &pending, padgrp->size) in intel_gpio_irq()
1300 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); in intel_gpio_irq()
1316 for (gpp = 0; gpp < community->ngpps; gpp++) { in intel_gpio_irq_init()
1317 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq_init()
1318 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_init()
1348 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in intel_gpio_add_pin_ranges()
1349 grp->gpio_base, grp->base, in intel_gpio_add_pin_ranges()
1350 grp->size); in intel_gpio_add_pin_ranges()
1352 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); in intel_gpio_add_pin_ranges()
1367 if (grp->gpio_base + grp->size > ngpio) in intel_gpio_ngpio()
1368 ngpio = grp->gpio_base + grp->size; in intel_gpio_ngpio()
1379 pctrl->chip = intel_gpio_chip; in intel_gpio_probe()
1382 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); in intel_gpio_probe()
1383 pctrl->chip.label = dev_name(pctrl->dev); in intel_gpio_probe()
1384 pctrl->chip.parent = pctrl->dev; in intel_gpio_probe()
1385 pctrl->chip.base = -1; in intel_gpio_probe()
1386 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; in intel_gpio_probe()
1387 pctrl->irq = irq; in intel_gpio_probe()
1393 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, in intel_gpio_probe()
1395 dev_name(pctrl->dev), pctrl); in intel_gpio_probe()
1397 dev_err(pctrl->dev, "failed to request interrupt\n"); in intel_gpio_probe()
1402 girq = &pctrl->chip.irq; in intel_gpio_probe()
1405 girq->parent_handler = NULL; in intel_gpio_probe()
1406 girq->num_parents = 0; in intel_gpio_probe()
1407 girq->default_type = IRQ_TYPE_NONE; in intel_gpio_probe()
1408 girq->handler = handle_bad_irq; in intel_gpio_probe()
1409 girq->init_hw = intel_gpio_irq_init_hw; in intel_gpio_probe()
1411 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); in intel_gpio_probe()
1413 dev_err(pctrl->dev, "failed to register gpiochip\n"); in intel_gpio_probe()
1425 size_t i, ngpps = community->ngpps; in intel_pinctrl_add_padgroups_by_gpps()
1427 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_gpps()
1429 return -ENOMEM; in intel_pinctrl_add_padgroups_by_gpps()
1432 gpps[i] = community->gpps[i]; in intel_pinctrl_add_padgroups_by_gpps()
1435 return -EINVAL; in intel_pinctrl_add_padgroups_by_gpps()
1455 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_gpps()
1464 unsigned int npins = community->npins; in intel_pinctrl_add_padgroups_by_size()
1466 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); in intel_pinctrl_add_padgroups_by_size()
1468 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) in intel_pinctrl_add_padgroups_by_size()
1469 return -EINVAL; in intel_pinctrl_add_padgroups_by_size()
1471 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_size()
1473 return -ENOMEM; in intel_pinctrl_add_padgroups_by_size()
1476 unsigned int gpp_size = community->gpp_size; in intel_pinctrl_add_padgroups_by_size()
1479 gpps[i].base = community->pin_base + i * gpp_size; in intel_pinctrl_add_padgroups_by_size()
1481 npins -= gpps[i].size; in intel_pinctrl_add_padgroups_by_size()
1486 padown_num += community->gpp_num_padown_regs; in intel_pinctrl_add_padgroups_by_size()
1489 community->ngpps = ngpps; in intel_pinctrl_add_padgroups_by_size()
1490 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_size()
1498 const struct intel_pinctrl_soc_data *soc = pctrl->soc; in intel_pinctrl_pm_init()
1503 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); in intel_pinctrl_pm_init()
1505 return -ENOMEM; in intel_pinctrl_pm_init()
1507 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, in intel_pinctrl_pm_init()
1510 return -ENOMEM; in intel_pinctrl_pm_init()
1513 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_pm_init()
1514 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_pm_init()
1517 intmask = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1520 return -ENOMEM; in intel_pinctrl_pm_init()
1524 hostown = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1527 return -ENOMEM; in intel_pinctrl_pm_init()
1532 pctrl->context.pads = pads; in intel_pinctrl_pm_init()
1533 pctrl->context.communities = communities; in intel_pinctrl_pm_init()
1549 if (!(community->features & PINCTRL_FEATURE_PWM)) in intel_pinctrl_probe_pwm()
1555 chip = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); in intel_pinctrl_probe_pwm()
1562 struct device *dev = &pdev->dev; in intel_pinctrl_probe()
1568 return -ENOMEM; in intel_pinctrl_probe()
1570 pctrl->dev = dev; in intel_pinctrl_probe()
1571 pctrl->soc = soc_data; in intel_pinctrl_probe()
1572 raw_spin_lock_init(&pctrl->lock); in intel_pinctrl_probe()
1578 pctrl->ncommunities = pctrl->soc->ncommunities; in intel_pinctrl_probe()
1579 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, in intel_pinctrl_probe()
1580 sizeof(*pctrl->communities), GFP_KERNEL); in intel_pinctrl_probe()
1581 if (!pctrl->communities) in intel_pinctrl_probe()
1582 return -ENOMEM; in intel_pinctrl_probe()
1584 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_probe()
1585 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_probe()
1590 *community = pctrl->soc->communities[i]; in intel_pinctrl_probe()
1592 regs = devm_platform_ioremap_resource(pdev, community->barno); in intel_pinctrl_probe()
1602 return -ENODEV; in intel_pinctrl_probe()
1604 community->features |= PINCTRL_FEATURE_DEBOUNCE; in intel_pinctrl_probe()
1605 community->features |= PINCTRL_FEATURE_1K_PD; in intel_pinctrl_probe()
1614 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; in intel_pinctrl_probe()
1617 community->features |= PINCTRL_FEATURE_PWM; in intel_pinctrl_probe()
1620 community->features |= PINCTRL_FEATURE_BLINK; in intel_pinctrl_probe()
1623 community->features |= PINCTRL_FEATURE_EXP; in intel_pinctrl_probe()
1631 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); in intel_pinctrl_probe()
1636 community->regs = regs; in intel_pinctrl_probe()
1637 community->pad_regs = regs + offset; in intel_pinctrl_probe()
1639 if (community->gpps) in intel_pinctrl_probe()
1659 pctrl->pctldesc = intel_pinctrl_desc; in intel_pinctrl_probe()
1660 pctrl->pctldesc.name = dev_name(dev); in intel_pinctrl_probe()
1661 pctrl->pctldesc.pins = pctrl->soc->pins; in intel_pinctrl_probe()
1662 pctrl->pctldesc.npins = pctrl->soc->npins; in intel_pinctrl_probe()
1664 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); in intel_pinctrl_probe()
1665 if (IS_ERR(pctrl->pctldev)) { in intel_pinctrl_probe()
1667 return PTR_ERR(pctrl->pctldev); in intel_pinctrl_probe()
1684 data = device_get_match_data(&pdev->dev); in intel_pinctrl_probe_by_hid()
1686 return -ENODATA; in intel_pinctrl_probe_by_hid()
1708 struct device *dev = &pdev->dev; in intel_pinctrl_get_soc_data()
1716 if (acpi_dev_uid_match(adev, table[i]->uid)) in intel_pinctrl_get_soc_data()
1725 return ERR_PTR(-ENODEV); in intel_pinctrl_get_soc_data()
1727 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; in intel_pinctrl_get_soc_data()
1728 data = table[pdev->id]; in intel_pinctrl_get_soc_data()
1731 return data ?: ERR_PTR(-ENODATA); in intel_pinctrl_get_soc_data()
1744 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); in intel_pinctrl_should_save()
1753 * BIOS during resume and those are not always locked down so leave in intel_pinctrl_should_save()
1756 if (pd->mux_owner || pd->gpio_owner || in intel_pinctrl_should_save()
1757 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) in intel_pinctrl_should_save()
1788 pads = pctrl->context.pads; in intel_pinctrl_suspend_noirq()
1789 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_suspend_noirq()
1790 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_suspend_noirq()
1794 if (!intel_pinctrl_should_save(pctrl, desc->number)) in intel_pinctrl_suspend_noirq()
1797 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); in intel_pinctrl_suspend_noirq()
1799 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); in intel_pinctrl_suspend_noirq()
1802 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); in intel_pinctrl_suspend_noirq()
1807 communities = pctrl->context.communities; in intel_pinctrl_suspend_noirq()
1808 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_suspend_noirq()
1809 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_suspend_noirq()
1813 base = community->regs + community->ie_offset; in intel_pinctrl_suspend_noirq()
1814 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1817 base = community->regs + community->hostown_offset; in intel_pinctrl_suspend_noirq()
1818 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1842 const struct intel_community *community = &pctrl->communities[c]; in intel_restore_hostown()
1843 const struct intel_padgroup *padgrp = &community->gpps[gpp]; in intel_restore_hostown()
1844 struct device *dev = pctrl->dev; in intel_restore_hostown()
1849 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_restore_hostown()
1852 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) in intel_restore_hostown()
1864 struct device *dev = pctrl->dev; in intel_restore_intmask()
1877 struct device *dev = pctrl->dev; in intel_restore_padcfg()
1900 pads = pctrl->context.pads; in intel_pinctrl_resume_noirq()
1901 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_resume_noirq()
1902 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_resume_noirq()
1904 if (!(intel_pinctrl_should_save(pctrl, desc->number) || in intel_pinctrl_resume_noirq()
1912 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); in intel_pinctrl_resume_noirq()
1913 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); in intel_pinctrl_resume_noirq()
1914 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); in intel_pinctrl_resume_noirq()
1917 communities = pctrl->context.communities; in intel_pinctrl_resume_noirq()
1918 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_resume_noirq()
1919 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_resume_noirq()
1923 base = community->regs + community->ie_offset; in intel_pinctrl_resume_noirq()
1924 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()
1927 base = community->regs + community->hostown_offset; in intel_pinctrl_resume_noirq()
1928 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()