Lines Matching +full:ras +full:- +full:to +full:- +full:cas
6 * This is a group-only pin controller.
20 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-utils.h"
27 #define DRIVER_NAME "pinctrl-gemini"
30 * struct gemini_pin_conf - information about configuring a pin
42 * struct gemini_pmx - state holder for the gemini pin controller
43 * @dev: a pointer back to containing device
44 * @virtbase: the offset to the controller in virtual memory
45 * @map: regmap to access registers
65 * struct gemini_pin_group - describes a Gemini pin group
68 * from the driver-local pin enumeration space
71 * @mask: bits to clear to enable this when doing pin muxing
72 * @value: bits to set to enable this when doing pin muxing
86 /* Some straight-forward control registers */
99 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
102 * - For the bits named *_DISABLE, once you enable something, it cannot be
201 PINCTRL_PIN(46, "C11 DRAM CAS N"),
220 PINCTRL_PIN(64, "D11 DRAM RAS N"),
553 * PCI needs to be active at the same time.
587 305, /* UART_NRTS RTS request to send */
588 287, /* UART_NCTS CTS clear to send */
613 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
621 * The parallel flash can be set up in a 26-bit address bus mode exposing
622 * A[0-15] (A[15] takes the place of ALE), but it has the
641 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
644 /* The GPIO0C (5-7) pins overlap with ICE */
650 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
671 /* The GPIO0L (26-29) pins overlap with parallel flash */
677 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
680 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
685 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
691 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
694 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
697 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
700 /* The GPIO2C (8-31) pins overlap with PCI */
841 * The construction is done such that it is possible to use a serial
843 * possible to use NAND and parallel flash together. To use serial
844 * flash with one of the two others, the muxbits need to be flipped
1096 PINCTRL_PIN(74, "D15 DRAM RAS N"),
1502 * PCI needs to be active at the same time.
1536 398, /* UART_NRTS RTS request to send */
1537 316, /* UART_NCTS CTS clear to send */
1562 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1570 * The parallel flash can be set up in a 26-bit address bus mode exposing
1571 * A[0-15] (A[15] takes the place of ALE), but it has the
1587 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1590 /* The GPIO0B (5-7) pins overlap with ICE */
1593 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1605 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1623 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1626 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1629 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1635 /* The GPIO1D (28-31) pins overlap with TVC */
1638 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1641 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1644 /* The GPIO2C (8-31) pins overlap with PCI */
1791 * The construction is done such that it is possible to use a serial
1793 * possible to use NAND and parallel flash together. To use serial
1794 * flash with one of the two others, the muxbits need to be flipped
1963 if (pmx->is_3512) in gemini_get_groups_count()
1965 if (pmx->is_3516) in gemini_get_groups_count()
1975 if (pmx->is_3512) in gemini_get_group_name()
1977 if (pmx->is_3516) in gemini_get_group_name()
1990 if (pmx->flash_pin && in gemini_get_group_pins()
1991 pmx->is_3512 && in gemini_get_group_pins()
1997 if (pmx->flash_pin && in gemini_get_group_pins()
1998 pmx->is_3516 && in gemini_get_group_pins()
2004 if (pmx->is_3512) { in gemini_get_group_pins()
2008 if (pmx->is_3516) { in gemini_get_group_pins()
2031 * struct gemini_pmx_func - describes Gemini pinmux functions
2204 if (pmx->is_3512) in gemini_pmx_set_mux()
2206 else if (pmx->is_3516) in gemini_pmx_set_mux()
2209 dev_err(pmx->dev, "invalid SoC type\n"); in gemini_pmx_set_mux()
2210 return -ENODEV; in gemini_pmx_set_mux()
2213 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2215 func->name, grp->name); in gemini_pmx_set_mux()
2217 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); in gemini_pmx_set_mux()
2218 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, in gemini_pmx_set_mux()
2219 grp->mask | grp->value, in gemini_pmx_set_mux()
2220 grp->value); in gemini_pmx_set_mux()
2221 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); in gemini_pmx_set_mux()
2226 expected = before &= ~grp->mask; in gemini_pmx_set_mux()
2227 expected |= grp->value; in gemini_pmx_set_mux()
2231 tmp = grp->mask; in gemini_pmx_set_mux()
2237 dev_err(pmx->dev, in gemini_pmx_set_mux()
2242 dev_err(pmx->dev, in gemini_pmx_set_mux()
2246 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2253 tmp = grp->value; in gemini_pmx_set_mux()
2259 dev_err(pmx->dev, in gemini_pmx_set_mux()
2264 dev_err(pmx->dev, in gemini_pmx_set_mux()
2268 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2372 for (i = 0; i < pmx->nconfs; i++) { in gemini_get_pin_conf()
2373 retconf = &pmx->confs[i]; in gemini_get_pin_conf()
2374 if (retconf->pin == pin) in gemini_get_pin_conf()
2392 return -ENOTSUPP; in gemini_pinconf_get()
2393 regmap_read(pmx->map, conf->reg, &val); in gemini_pinconf_get()
2394 val &= conf->mask; in gemini_pinconf_get()
2395 val >>= (ffs(conf->mask) - 1); in gemini_pinconf_get()
2399 return -ENOTSUPP; in gemini_pinconf_get()
2422 return -EINVAL; in gemini_pinconf_set()
2425 dev_err(pmx->dev, in gemini_pinconf_set()
2427 return -ENOTSUPP; in gemini_pinconf_set()
2429 arg <<= (ffs(conf->mask) - 1); in gemini_pinconf_set()
2430 dev_dbg(pmx->dev, in gemini_pinconf_set()
2431 "set pin %d to skew delay mask %08x, val %08x\n", in gemini_pinconf_set()
2432 pin, conf->mask, arg); in gemini_pinconf_set()
2433 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); in gemini_pinconf_set()
2436 dev_err(pmx->dev, "Invalid config param %04x\n", param); in gemini_pinconf_set()
2437 return -ENOTSUPP; in gemini_pinconf_set()
2456 if (pmx->is_3512) in gemini_pinconf_group_set()
2458 if (pmx->is_3516) in gemini_pinconf_group_set()
2462 if (!grp->driving_mask) { in gemini_pinconf_group_set()
2463 dev_err(pmx->dev, "pin config group \"%s\" does " in gemini_pinconf_group_set()
2465 grp->name); in gemini_pinconf_group_set()
2466 return -EINVAL; in gemini_pinconf_group_set()
2489 dev_err(pmx->dev, in gemini_pinconf_group_set()
2492 return -ENOTSUPP; in gemini_pinconf_group_set()
2494 val <<= (ffs(grp->driving_mask) - 1); in gemini_pinconf_group_set()
2495 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, in gemini_pinconf_group_set()
2496 grp->driving_mask, in gemini_pinconf_group_set()
2498 dev_dbg(pmx->dev, in gemini_pinconf_group_set()
2499 "set group %s to %d mA drive strength mask %08x val %08x\n", in gemini_pinconf_group_set()
2500 grp->name, arg, grp->driving_mask, val); in gemini_pinconf_group_set()
2503 dev_err(pmx->dev, "invalid config param %04x\n", param); in gemini_pinconf_group_set()
2504 return -ENOTSUPP; in gemini_pinconf_group_set()
2530 struct device *dev = &pdev->dev; in gemini_pmx_probe()
2538 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in gemini_pmx_probe()
2540 return -ENOMEM; in gemini_pmx_probe()
2542 pmx->dev = &pdev->dev; in gemini_pmx_probe()
2543 parent = dev->parent; in gemini_pmx_probe()
2545 dev_err(dev, "no parent to pin controller\n"); in gemini_pmx_probe()
2546 return -ENODEV; in gemini_pmx_probe()
2548 map = syscon_node_to_regmap(parent->of_node); in gemini_pmx_probe()
2553 pmx->map = map; in gemini_pmx_probe()
2564 pmx->is_3512 = true; in gemini_pmx_probe()
2565 pmx->confs = gemini_confs_3512; in gemini_pmx_probe()
2566 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); in gemini_pmx_probe()
2571 pmx->is_3516 = true; in gemini_pmx_probe()
2572 pmx->confs = gemini_confs_3516; in gemini_pmx_probe()
2573 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); in gemini_pmx_probe()
2579 return -ENODEV; in gemini_pmx_probe()
2597 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); in gemini_pmx_probe()
2598 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); in gemini_pmx_probe()
2600 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); in gemini_pmx_probe()
2601 if (IS_ERR(pmx->pctl)) { in gemini_pmx_probe()
2603 return PTR_ERR(pmx->pctl); in gemini_pmx_probe()
2612 { .compatible = "cortina,gemini-pinctrl" },