88 			    const struct msm_pingroup *g) \
90 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
93 			      const struct msm_pingroup *g) \
95 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
105 				const struct msm_pingroup *g)  in MSM_ACCESSOR()
107 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;  in MSM_ACCESSOR()
109 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
192 	const struct msm_pingroup *g;  in msm_pinmux_set_mux()  local
197 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
198 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);  in msm_pinmux_set_mux()
200 	for (i = 0; i < g->nfuncs; i++) {  in msm_pinmux_set_mux()
201 		if (g->funcs[i] == function)  in msm_pinmux_set_mux()
205 	if (WARN_ON(i == g->nfuncs))  in msm_pinmux_set_mux()
224 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
232 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&  in msm_pinmux_set_mux()
234 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
236 		if (io_val & BIT(g->in_bit)) {  in msm_pinmux_set_mux()
237 			if (!(io_val & BIT(g->out_bit)))  in msm_pinmux_set_mux()
238 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
240 			if (io_val & BIT(g->out_bit))  in msm_pinmux_set_mux()
241 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
246 		if (val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
247 			val &= ~BIT(g->egpio_enable);  in msm_pinmux_set_mux()
250 		val |= i << g->mux_bit;  in msm_pinmux_set_mux()
252 		if (egpio_func && val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
253 			val |= BIT(g->egpio_enable);  in msm_pinmux_set_mux()
256 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
269 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
282 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()  local
285 	if (!g->nfuncs)  in msm_pinmux_request_gpio()
288 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
301 			  const struct msm_pingroup *g,  in msm_config_reg()  argument
311 		*bit = g->pull_bit;  in msm_config_reg()
313 		if (g->i2c_pull_bit)  in msm_config_reg()
314 			*mask |= BIT(g->i2c_pull_bit) >> *bit;  in msm_config_reg()
317 		*bit = g->od_bit;  in msm_config_reg()
321 		*bit = g->drv_bit;  in msm_config_reg()
327 		*bit = g->oe_bit;  in msm_config_reg()
353 	const struct msm_pingroup *g;  in msm_config_group_get()  local
366 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
368 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
372 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
398 		else if (arg & BIT(g->i2c_pull_bit))  in msm_config_group_get()
419 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
420 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
440 	const struct msm_pingroup *g;  in msm_config_group_set()  local
451 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
457 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
478 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)  in msm_config_group_set()
479 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;  in msm_config_group_set()
496 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
498 				val |= BIT(g->out_bit);  in msm_config_group_set()
500 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
501 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
551 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
554 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
569 	const struct msm_pingroup *g;  in msm_gpio_direction_input()  local
574 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
578 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
579 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
580 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
589 	const struct msm_pingroup *g;  in msm_gpio_direction_output()  local
594 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
598 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
600 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
602 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
603 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
605 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
606 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
607 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
617 	const struct msm_pingroup *g;  in msm_gpio_get_direction()  local
620 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
622 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
624 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :  in msm_gpio_get_direction()
630 	const struct msm_pingroup *g;  in msm_gpio_get()  local
634 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
636 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
637 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
642 	const struct msm_pingroup *g;  in msm_gpio_set()  local
647 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
651 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
653 		val |= BIT(g->out_bit);  in msm_gpio_set()
655 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
656 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
669 	const struct msm_pingroup *g;  in msm_gpio_dbg_show_one()  local
695 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
696 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
697 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
699 	is_out = !!(ctl_reg & BIT(g->oe_bit));  in msm_gpio_dbg_show_one()
700 	func = (ctl_reg >> g->mux_bit) & 7;  in msm_gpio_dbg_show_one()
701 	drive = (ctl_reg >> g->drv_bit) & 7;  in msm_gpio_dbg_show_one()
702 	pull = (ctl_reg >> g->pull_bit) & 3;  in msm_gpio_dbg_show_one()
704 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
705 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));  in msm_gpio_dbg_show_one()
708 		val = !!(io_reg & BIT(g->out_bit));  in msm_gpio_dbg_show_one()
710 		val = !!(io_reg & BIT(g->in_bit));  in msm_gpio_dbg_show_one()
713 		seq_printf(s, " %-8s: egpio\n", g->grp.name);  in msm_gpio_dbg_show_one()
717 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");  in msm_gpio_dbg_show_one()
822 					  const struct msm_pingroup *g,  in msm_gpio_update_dual_edge_pos()  argument
830 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
832 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
833 		pol ^= BIT(g->intr_polarity_bit);  in msm_gpio_update_dual_edge_pos()
834 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
836 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
837 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
849 	const struct msm_pingroup *g;  in msm_gpio_irq_mask()  local
859 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
863 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
885 		val &= ~BIT(g->intr_raw_status_bit);  in msm_gpio_irq_mask()
887 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
888 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
899 	const struct msm_pingroup *g;  in msm_gpio_irq_unmask()  local
909 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
913 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
914 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_unmask()
915 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
916 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
964 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()  local
970 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
983 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
1001 	const struct msm_pingroup *g;  in msm_gpio_irq_ack()  local
1010 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
1014 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
1017 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1045 	const struct msm_pingroup *g;  in msm_gpio_irq_set_type()  local
1066 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1073 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)  in msm_gpio_irq_set_type()
1082 	if (g->intr_target_width)  in msm_gpio_irq_set_type()
1083 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);  in msm_gpio_irq_set_type()
1086 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1090 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1091 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1099 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1100 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1101 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1102 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1110 	val = oldval = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1111 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1112 	if (g->intr_detection_width == 2) {  in msm_gpio_irq_set_type()
1113 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1114 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1117 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1118 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1121 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1122 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1125 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1126 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1131 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1134 	} else if (g->intr_detection_width == 1) {  in msm_gpio_irq_set_type()
1135 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1136 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1139 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1140 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1143 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1146 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1147 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1152 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1158 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1168 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1171 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1204 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_reqres()  local
1239 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_reqres()
1244 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_reqres()
1245 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_reqres()
1246 			intr_cfg |= BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_reqres()
1247 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_reqres()
1263 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_relres()  local
1267 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_relres()
1272 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_relres()
1273 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_relres()
1274 			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_relres()
1275 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_relres()
1311 	const struct msm_pingroup *g;  in msm_gpio_irq_handler()  local
1325 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1326 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1327 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()