87 #define OMAP_PRM_HAS_RSTCTRL	BIT(0)
138 	{ .rst = 0, .st = 0 },
143 	{ .rst = 0, .st = 0 },
149 	{ .rst = 0, .st = 0 },
157 		.name = "mpu", .base = 0x4a306300,
158 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
161 		.name = "tesla", .base = 0x4a306400,
162 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
163 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
166 		.name = "abe", .base = 0x4a306500,
167 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
170 		.name = "always_on_core", .base = 0x4a306600,
171 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
174 		.name = "core", .base = 0x4a306700,
175 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
176 		.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
181 		.name = "ivahd", .base = 0x4a306f00,
182 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
183 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
186 		.name = "cam", .base = 0x4a307000,
187 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
190 		.name = "dss", .base = 0x4a307100,
191 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
194 		.name = "gfx", .base = 0x4a307200,
195 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
198 		.name = "l3init", .base = 0x4a307300,
199 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
202 		.name = "l4per", .base = 0x4a307400,
203 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
207 		.name = "cefuse", .base = 0x4a307600,
208 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
211 		.name = "wkup", .base = 0x4a307700,
212 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
215 		.name = "emu", .base = 0x4a307900,
216 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
219 		.name = "device", .base = 0x4a307b00,
220 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
228 		.name = "mpu", .base = 0x4ae06300,
229 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
232 		.name = "dsp", .base = 0x4ae06400,
233 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
234 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
237 		.name = "abe", .base = 0x4ae06500,
238 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
241 		.name = "coreaon", .base = 0x4ae06600,
242 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
245 		.name = "core", .base = 0x4ae06700,
246 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
247 		.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu",
251 		.name = "iva", .base = 0x4ae07200,
252 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
253 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
256 		.name = "cam", .base = 0x4ae07300,
257 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
260 		.name = "dss", .base = 0x4ae07400,
261 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
264 		.name = "gpu", .base = 0x4ae07500,
265 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
268 		.name = "l3init", .base = 0x4ae07600,
269 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
272 		.name = "custefuse", .base = 0x4ae07700,
273 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
276 		.name = "wkupaon", .base = 0x4ae07800,
277 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
280 		.name = "emu", .base = 0x4ae07a00,
281 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
284 		.name = "device", .base = 0x4ae07c00,
285 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
293 		.name = "mpu", .base = 0x4ae06300,
294 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
297 		.name = "dsp1", .base = 0x4ae06400,
298 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
299 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
302 		.name = "ipu", .base = 0x4ae06500,
303 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
304 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
308 		.name = "coreaon", .base = 0x4ae06628,
309 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
312 		.name = "core", .base = 0x4ae06700,
313 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
314 		.rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
318 		.name = "iva", .base = 0x4ae06f00,
319 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
320 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
323 		.name = "cam", .base = 0x4ae07000,
324 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
327 		.name = "dss", .base = 0x4ae07100,
328 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
331 		.name = "gpu", .base = 0x4ae07200,
332 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
335 		.name = "l3init", .base = 0x4ae07300,
336 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
337 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
341 		.name = "l4per", .base = 0x4ae07400,
342 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
345 		.name = "custefuse", .base = 0x4ae07600,
346 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
349 		.name = "wkupaon", .base = 0x4ae07724,
350 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
353 		.name = "emu", .base = 0x4ae07900,
354 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
357 		.name = "dsp2", .base = 0x4ae07b00,
358 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
359 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
362 		.name = "eve1", .base = 0x4ae07b40,
363 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
364 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
367 		.name = "eve2", .base = 0x4ae07b80,
368 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
369 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
372 		.name = "eve3", .base = 0x4ae07bc0,
373 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
374 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
377 		.name = "eve4", .base = 0x4ae07c00,
378 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
379 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
382 		.name = "rtc", .base = 0x4ae07c60,
383 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
386 		.name = "vpe", .base = 0x4ae07c80,
387 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
404 		.name = "per", .base = 0x44e00c00,
405 		.pwrstctrl = 0xc, .pwrstst = 0x8, .dmap = &omap_prm_noinact,
406 		.rstctrl = 0x0, .rstmap = am3_per_rst_map,
410 		.name = "wkup", .base = 0x44e00d00,
411 		.pwrstctrl = 0x4, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
412 		.rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map,
416 		.name = "mpu", .base = 0x44e00e00,
417 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
420 		.name = "device", .base = 0x44e00f00,
421 		.rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01,
425 		.name = "rtc", .base = 0x44e01000,
426 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
429 		.name = "gfx", .base = 0x44e01100,
430 		.pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact,
431 		.rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
434 		.name = "cefuse", .base = 0x44e01200,
435 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
441 	{ .rst = 1, .st = 0 },
446 	{ .rst = 0, .st = 1 },
447 	{ .rst = 1, .st = 0 },
453 		.name = "mpu", .base = 0x44df0300,
454 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
457 		.name = "gfx", .base = 0x44df0400,
458 		.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
459 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
462 		.name = "rtc", .base = 0x44df0500,
463 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
466 		.name = "tamper", .base = 0x44df0600,
467 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
470 		.name = "cefuse", .base = 0x44df0700,
471 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
474 		.name = "per", .base = 0x44df0800,
475 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
476 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map,
480 		.name = "wkup", .base = 0x44df2000,
481 		.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
482 		.rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map,
486 		.name = "device", .base = 0x44df4000,
487 		.rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map,
526 		return 0;  in omap_prm_domain_power_on()
570 		return 0;  in omap_prm_domain_power_off()
599 	return 0;  in omap_prm_domain_power_off()
614 		return 0;  in omap_prm_domain_attach_clock()
617 		return 0;  in omap_prm_domain_attach_clock()
624 	if (error < 0) {  in omap_prm_domain_attach_clock()
631 	return 0;  in omap_prm_domain_attach_clock()
647 					 "#power-domain-cells", 0, &pd_args);  in omap_prm_domain_attach_dev()
648 	if (ret < 0)  in omap_prm_domain_attach_dev()
651 	if (pd_args.args_count != 0)  in omap_prm_domain_attach_dev()
662 	return 0;  in omap_prm_domain_attach_dev()
687 		return 0;  in omap_prm_domain_init()
737 	while (map->rst >= 0) {  in omap_reset_get_st_bit()
767 	 * completed successfully so we can return 0 here (reset deasserted)  in omap_reset_status()
790 	return 0;  in omap_reset_assert()
802 	int ret = 0;  in omap_reset_deassert()
806 		return 0;  in omap_reset_deassert()
866 	if (!_is_valid_reset(reset, reset_spec->args[0]))  in omap_prm_reset_xlate()
869 	return reset_spec->args[0];  in omap_prm_reset_xlate()
887 		return 0;  in omap_prm_reset_init()
922 	while (map->rst >= 0) {  in omap_prm_reset_init()
955 	prm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in omap_prm_probe()
975 	return 0;  in omap_prm_probe()