Lines Matching +full:num +full:- +full:lanes
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
31 unsigned int *lanes; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
56 ch = hweight32(p_rt->ch_mask); in sdw_compute_slave_ports()
58 sdw_fill_xport_params(&p_rt->transport_params, in sdw_compute_slave_ports()
59 p_rt->num, false, in sdw_compute_slave_ports()
62 t_data->hstart, in sdw_compute_slave_ports()
63 t_data->hstop, in sdw_compute_slave_ports()
64 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
66 sdw_fill_port_params(&p_rt->port_params, in sdw_compute_slave_ports()
67 p_rt->num, bps, in sdw_compute_slave_ports()
69 b_params->s_data_mode); in sdw_compute_slave_ports()
75 if (m_rt->direction == SDW_DATA_DIR_TX && in sdw_compute_slave_ports()
76 m_rt->ch_count == slave_total_ch) { in sdw_compute_slave_ports()
83 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
95 struct sdw_bus *bus = m_rt->bus; in sdw_compute_master_ports()
96 struct sdw_bus_params *b_params = &bus->params; in sdw_compute_master_ports()
100 rate = m_rt->stream->params.rate; in sdw_compute_master_ports()
101 bps = m_rt->stream->params.bps; in sdw_compute_master_ports()
102 ch = m_rt->ch_count; in sdw_compute_master_ports()
103 sample_int = (bus->params.curr_dr_freq / rate); in sdw_compute_master_ports()
105 if (rate != params->rate) in sdw_compute_master_ports()
109 hstart = hstop - params->hwidth + 1; in sdw_compute_master_ports()
112 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_compute_master_ports()
113 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
116 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, in sdw_compute_master_ports()
119 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
121 sdw_fill_port_params(&p_rt->port_params, in sdw_compute_master_ports()
122 p_rt->num, bps, in sdw_compute_master_ports()
124 b_params->m_data_mode); in sdw_compute_master_ports()
127 if (!(p_rt == list_first_entry(&m_rt->port_list, in sdw_compute_master_ports()
141 t_data.lane = params->lane; in sdw_compute_master_ports()
154 if (l > 0 && !bus->lane_used_bandwidth[l]) in _sdw_compute_port_params()
157 hstop = bus->params.col - 1; in _sdw_compute_port_params()
163 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in _sdw_compute_port_params()
167 hstop = hstop - params[i].hwidth; in _sdw_compute_port_params()
179 int sel_col = bus->params.col; in sdw_compute_group_params()
184 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
185 params[i].rate = group->rates[i]; in sdw_compute_group_params()
186 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
187 params[i].full_bw = bus->params.curr_dr_freq / params[i].rate; in sdw_compute_group_params()
190 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_compute_group_params()
191 if (m_rt->stream == stream) { in sdw_compute_group_params()
193 if (stream->state != SDW_STREAM_CONFIGURED) in sdw_compute_group_params()
200 if (m_rt->stream->state != SDW_STREAM_ENABLED && in sdw_compute_group_params()
201 m_rt->stream->state != SDW_STREAM_PREPARED && in sdw_compute_group_params()
202 m_rt->stream->state != SDW_STREAM_DISABLED) in sdw_compute_group_params()
205 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_compute_group_params()
206 rate = m_rt->stream->params.rate; in sdw_compute_group_params()
207 bps = m_rt->stream->params.bps; in sdw_compute_group_params()
208 ch = hweight32(p_rt->ch_mask); in sdw_compute_group_params()
210 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
211 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
218 if (l > 0 && !bus->lane_used_bandwidth[l]) in sdw_compute_group_params()
222 for (i = 0; i < group->count; i++) { in sdw_compute_group_params()
227 params[i].full_bw - 1) / params[i].full_bw; in sdw_compute_group_params()
232 return -EINVAL; in sdw_compute_group_params()
234 if (params[i].lane == 0 && column_needed > sel_col - 1) in sdw_compute_group_params()
235 return -EINVAL; in sdw_compute_group_params()
246 int num = group->count; in sdw_add_element_group_count() local
249 for (i = 0; i <= num; i++) { in sdw_add_element_group_count()
250 if (rate == group->rates[i] && lane == group->lanes[i]) in sdw_add_element_group_count()
253 if (i != num) in sdw_add_element_group_count()
256 if (group->count >= group->max_size) { in sdw_add_element_group_count()
258 unsigned int *lanes; in sdw_add_element_group_count() local
260 group->max_size += 1; in sdw_add_element_group_count()
261 rates = krealloc(group->rates, in sdw_add_element_group_count()
262 (sizeof(int) * group->max_size), in sdw_add_element_group_count()
265 return -ENOMEM; in sdw_add_element_group_count()
267 group->rates = rates; in sdw_add_element_group_count()
269 lanes = krealloc(group->lanes, in sdw_add_element_group_count()
270 (sizeof(int) * group->max_size), in sdw_add_element_group_count()
272 if (!lanes) in sdw_add_element_group_count()
273 return -ENOMEM; in sdw_add_element_group_count()
275 group->lanes = lanes; in sdw_add_element_group_count()
278 group->rates[group->count] = rate; in sdw_add_element_group_count()
279 group->lanes[group->count++] = lane; in sdw_add_element_group_count()
293 group->count = 0; in sdw_get_group_count()
294 group->max_size = SDW_STRM_RATE_GROUPING; in sdw_get_group_count()
295 group->rates = kcalloc(group->max_size, sizeof(int), GFP_KERNEL); in sdw_get_group_count()
296 if (!group->rates) in sdw_get_group_count()
297 return -ENOMEM; in sdw_get_group_count()
299 group->lanes = kcalloc(group->max_size, sizeof(int), GFP_KERNEL); in sdw_get_group_count()
300 if (!group->lanes) { in sdw_get_group_count()
301 kfree(group->rates); in sdw_get_group_count()
302 group->rates = NULL; in sdw_get_group_count()
303 return -ENOMEM; in sdw_get_group_count()
306 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_get_group_count()
307 if (m_rt->stream->state == SDW_STREAM_DEPREPARED) in sdw_get_group_count()
310 rate = m_rt->stream->params.rate; in sdw_get_group_count()
311 if (m_rt == list_first_entry(&bus->m_rt_list, in sdw_get_group_count()
314 group->rates[group->count++] = rate; in sdw_get_group_count()
320 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in sdw_get_group_count()
321 ret = sdw_add_element_group_count(group, rate, p_rt->lane); in sdw_get_group_count()
323 kfree(group->rates); in sdw_get_group_count()
324 kfree(group->lanes); in sdw_get_group_count()
354 ret = -ENOMEM; in sdw_compute_port_params()
369 kfree(group.lanes); in sdw_compute_port_params()
376 struct sdw_master_prop *prop = &bus->prop; in sdw_select_row_col()
381 if (sdw_rows[r] != prop->default_row || in sdw_select_row_col()
382 sdw_cols[c] != prop->default_col) in sdw_select_row_col()
385 if (clk_freq * (sdw_cols[c] - 1) < in sdw_select_row_col()
386 bus->params.bandwidth * sdw_cols[c]) in sdw_select_row_col()
389 bus->params.row = sdw_rows[r]; in sdw_select_row_col()
390 bus->params.col = sdw_cols[c]; in sdw_select_row_col()
395 return -EINVAL; in sdw_select_row_col()
403 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) in is_clock_scaling_supported()
404 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) in is_clock_scaling_supported()
405 if (!is_clock_scaling_supported_by_slave(s_rt->slave)) in is_clock_scaling_supported()
424 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in is_lane_connected_to_all_peripherals()
425 slave_prop = &s_rt->slave->prop; in is_lane_connected_to_all_peripherals()
427 if (slave_prop->lane_maps[i] == lane) { in is_lane_connected_to_all_peripherals()
428 dev_dbg(&s_rt->slave->dev, in is_lane_connected_to_all_peripherals()
435 dev_dbg(&s_rt->slave->dev, "M lane %d is not connected\n", lane); in is_lane_connected_to_all_peripherals()
445 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop; in get_manager_lane()
452 if (!slave_prop->lane_maps[l]) in get_manager_lane()
456 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) { in get_manager_lane()
457 required_bandwidth += m_rt->stream->params.rate * in get_manager_lane()
458 hweight32(m_p_rt->ch_mask) * in get_manager_lane()
459 m_rt->stream->params.bps; in get_manager_lane()
462 curr_dr_freq - bus->lane_used_bandwidth[l]) { in get_manager_lane()
465 slave_prop->lane_maps[l])) { in get_manager_lane()
466 dev_dbg(bus->dev, in get_manager_lane()
468 slave_prop->lane_maps[l]); in get_manager_lane()
471 m_lane = slave_prop->lane_maps[l]; in get_manager_lane()
472 dev_dbg(&s_rt->slave->dev, "M lane %d is used\n", m_lane); in get_manager_lane()
473 bus->lane_used_bandwidth[l] += required_bandwidth; in get_manager_lane()
475 * Use non-zero manager lane, subtract the lane 0 in get_manager_lane()
478 bus->params.bandwidth -= required_bandwidth; in get_manager_lane()
494 struct sdw_master_prop *mstr_prop = &bus->prop; in sdw_compute_bus_params()
506 if (mstr_prop->num_clk_gears) { in sdw_compute_bus_params()
507 clk_values = mstr_prop->num_clk_gears; in sdw_compute_bus_params()
508 clk_buf = mstr_prop->clk_gears; in sdw_compute_bus_params()
510 } else if (mstr_prop->num_clk_freq) { in sdw_compute_bus_params()
511 clk_values = mstr_prop->num_clk_freq; in sdw_compute_bus_params()
512 clk_buf = mstr_prop->clk_freq; in sdw_compute_bus_params()
524 curr_dr_freq = bus->params.max_dr_freq; in sdw_compute_bus_params()
527 (bus->params.max_dr_freq >> clk_buf[i]) : in sdw_compute_bus_params()
530 if (curr_dr_freq * (mstr_prop->default_col - 1) >= in sdw_compute_bus_params()
531 bus->params.bandwidth * mstr_prop->default_col) in sdw_compute_bus_params()
534 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in sdw_compute_bus_params()
538 * multi-lane if we can't find any available lane for the first Peripheral. in sdw_compute_bus_params()
540 s_rt = list_first_entry(&m_rt->slave_rt_list, in sdw_compute_bus_params()
559 dev_err(bus->dev, "%s: could not find clock value for bandwidth %d\n", in sdw_compute_bus_params()
560 __func__, bus->params.bandwidth); in sdw_compute_bus_params()
561 return -EINVAL; in sdw_compute_bus_params()
566 /* Set Peripheral lanes */ in sdw_compute_bus_params()
567 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_bus_params()
568 slave_prop = &s_rt->slave->prop; in sdw_compute_bus_params()
570 if (slave_prop->lane_maps[l] == m_lane) { in sdw_compute_bus_params()
571 list_for_each_entry(s_p_rt, &s_rt->port_list, port_node) { in sdw_compute_bus_params()
572 s_p_rt->lane = l; in sdw_compute_bus_params()
573 dev_dbg(&s_rt->slave->dev, in sdw_compute_bus_params()
575 l, s_p_rt->num); in sdw_compute_bus_params()
582 * Set Manager lanes. Configure the last m_rt in bus->m_rt_list only since in sdw_compute_bus_params()
585 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) { in sdw_compute_bus_params()
586 m_p_rt->lane = m_lane; in sdw_compute_bus_params()
590 if (!mstr_prop->default_frame_rate || !mstr_prop->default_row) in sdw_compute_bus_params()
591 return -EINVAL; in sdw_compute_bus_params()
593 mstr_prop->default_col = curr_dr_freq / mstr_prop->default_frame_rate / in sdw_compute_bus_params()
594 mstr_prop->default_row; in sdw_compute_bus_params()
598 dev_err(bus->dev, "%s: could not find frame configuration for bus dr_freq %d\n", in sdw_compute_bus_params()
600 return -EINVAL; in sdw_compute_bus_params()
603 bus->params.curr_dr_freq = curr_dr_freq; in sdw_compute_bus_params()
625 dev_err(bus->dev, "Compute transport params failed: %d\n", ret); in sdw_compute_params()