116 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)  in mchp_corespi_read()  function
128 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_disable()
140 		while (mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)  in mchp_corespi_read_fifo()
143 		data = mchp_corespi_read(spi, REG_RX_DATA);  in mchp_corespi_read_fifo()
163 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_enable_ints()
171 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_disable_ints()
181 	u32 frames = mchp_corespi_read(spi, REG_FRAMESUP);  in mchp_corespi_set_xfer_size()
211 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_xfer_size()
224 	while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {  in mchp_corespi_write_fifo()
245 	u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE);  in mchp_corespi_set_framesize()
255 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_framesize()
270 	reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);  in mchp_corespi_set_cs()
301 		reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);  in mchp_corespi_setup()
312 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_init()
349 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_init()
361 	control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_clk_gen()
374 	u32 control = mchp_corespi_read(spi, REG_CONTROL);  in mchp_corespi_set_mode()
412 	u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;  in mchp_corespi_interrupt()