427 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,  in stm32_spi_clr_bits()  function
450 	stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);  in stm32h7_spi_get_fifo_size()
739 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);  in stm32f7_spi_read_rx()
825 	stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXEIE |  in stm32fx_spi_disable()
841 	stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE);  in stm32fx_spi_disable()
843 	stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN |  in stm32fx_spi_disable()
884 	stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);  in stm32h7_spi_disable()
886 	stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |  in stm32h7_spi_disable()
999 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR2,  in stm32fx_spi_irq_event()
1396 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);  in stm32f7_spi_transfer_one_dma_start()
1516 	stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,  in stm32_spi_transfer_one_dma()
1536 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF);  in stm32f4_spi_set_bpw()
1651 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,  in stm32fx_spi_set_mode()
1657 		stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,  in stm32fx_spi_set_mode()
1678 		stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);  in stm32h7_spi_set_mode()
1888 	stm32_spi_clr_bits(spi, STM32FX_SPI_I2SCFGR,  in stm32fx_spi_config()
1920 	stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,  in stm32h7_spi_config()