Lines Matching +full:0 +full:xc400
55 #define DWC3_EVENT_TYPE_MASK 0xfe
57 #define DWC3_EVENT_TYPE_DEV 0
61 #define DWC3_DEVICE_EVENT_DISCONNECT 0
74 #define DWC3_OTG_ROLE_IDLE 0
78 #define DWC3_GEVNTCOUNT_MASK 0xfffc
80 #define DWC3_GSNPSID_MASK 0xffff0000
81 #define DWC3_GSNPSREV_MASK 0xffff
85 #define DWC3_XHCI_REGS_START 0x0
86 #define DWC3_XHCI_REGS_END 0x7fff
87 #define DWC3_GLOBALS_REGS_START 0xc100
88 #define DWC3_GLOBALS_REGS_END 0xc6ff
89 #define DWC3_DEVICE_REGS_START 0xc700
90 #define DWC3_DEVICE_REGS_END 0xcbff
91 #define DWC3_OTG_REGS_START 0xcc00
92 #define DWC3_OTG_REGS_END 0xccff
94 #define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100
97 #define DWC3_GSBUSCFG0 0xc100
98 #define DWC3_GSBUSCFG1 0xc104
99 #define DWC3_GTXTHRCFG 0xc108
100 #define DWC3_GRXTHRCFG 0xc10c
101 #define DWC3_GCTL 0xc110
102 #define DWC3_GEVTEN 0xc114
103 #define DWC3_GSTS 0xc118
104 #define DWC3_GUCTL1 0xc11c
105 #define DWC3_GSNPSID 0xc120
106 #define DWC3_GGPIO 0xc124
107 #define DWC3_GUID 0xc128
108 #define DWC3_GUCTL 0xc12c
109 #define DWC3_GBUSERRADDR0 0xc130
110 #define DWC3_GBUSERRADDR1 0xc134
111 #define DWC3_GPRTBIMAP0 0xc138
112 #define DWC3_GPRTBIMAP1 0xc13c
113 #define DWC3_GHWPARAMS0 0xc140
114 #define DWC3_GHWPARAMS1 0xc144
115 #define DWC3_GHWPARAMS2 0xc148
116 #define DWC3_GHWPARAMS3 0xc14c
117 #define DWC3_GHWPARAMS4 0xc150
118 #define DWC3_GHWPARAMS5 0xc154
119 #define DWC3_GHWPARAMS6 0xc158
120 #define DWC3_GHWPARAMS7 0xc15c
121 #define DWC3_GDBGFIFOSPACE 0xc160
122 #define DWC3_GDBGLTSSM 0xc164
123 #define DWC3_GDBGBMU 0xc16c
124 #define DWC3_GDBGLSPMUX 0xc170
125 #define DWC3_GDBGLSP 0xc174
126 #define DWC3_GDBGEPINFO0 0xc178
127 #define DWC3_GDBGEPINFO1 0xc17c
128 #define DWC3_GPRTBIMAP_HS0 0xc180
129 #define DWC3_GPRTBIMAP_HS1 0xc184
130 #define DWC3_GPRTBIMAP_FS0 0xc188
131 #define DWC3_GPRTBIMAP_FS1 0xc18c
132 #define DWC3_GUCTL2 0xc19c
134 #define DWC3_VER_NUMBER 0xc1a0
135 #define DWC3_VER_TYPE 0xc1a4
137 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
138 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
140 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
142 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
144 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
145 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
147 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
148 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
149 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
150 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
152 #define DWC3_GHWPARAMS8 0xc600
153 #define DWC3_GUCTL3 0xc60c
154 #define DWC3_GFLADJ 0xc630
155 #define DWC3_GHWPARAMS9 0xc6e0
158 #define DWC3_DCFG 0xc700
159 #define DWC3_DCTL 0xc704
160 #define DWC3_DEVTEN 0xc708
161 #define DWC3_DSTS 0xc70c
162 #define DWC3_DGCMDPAR 0xc710
163 #define DWC3_DGCMD 0xc714
164 #define DWC3_DALEPENA 0xc720
165 #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */
167 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
168 #define DWC3_DEPCMDPAR2 0x00
169 #define DWC3_DEPCMDPAR1 0x04
170 #define DWC3_DEPCMDPAR0 0x08
171 #define DWC3_DEPCMD 0x0c
173 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
176 #define DWC3_OCFG 0xcc00
177 #define DWC3_OCTL 0xcc04
178 #define DWC3_OEVT 0xcc08
179 #define DWC3_OEVTEN 0xcc0C
180 #define DWC3_OSTS 0xcc10
182 #define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80))
186 /* Global SoC Bus Configuration INCRx Register 0 */
194 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
195 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
198 #define DWC3_GSBUSCFG0_REQINFO(n) (((n) & 0xffff) << 16)
199 #define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED 0xffffffff
203 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
204 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
205 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
208 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
209 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
210 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
212 #define DWC3_TXFIFO 0
223 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
224 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
228 #define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16)
229 #define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24)
233 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
234 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
237 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
239 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
240 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
243 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
244 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
247 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
249 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
250 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
257 #define DWC3_GCTL_CLK_BUS (0)
275 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
294 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
295 #define DWC3_GSTS_CURMOD_DEVICE 0
308 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
312 #define UTMI_PHYIF_8_BIT 0
321 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
341 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
342 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
343 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
346 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
347 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
351 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
354 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
355 #define DWC3_GHWPARAMS0_MODE_GADGET 0
358 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
359 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
360 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
361 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
362 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
366 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
375 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
379 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
384 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
388 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
400 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
403 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
404 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
407 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
412 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
419 #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
431 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
434 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
436 #define DWC3_DCFG_SPEED_MASK (7 << 0)
437 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
438 #define DWC3_DCFG_SUPERSPEED (4 << 0)
439 #define DWC3_DCFG_HIGHSPEED (0 << 0)
440 #define DWC3_DCFG_FULLSPEED BIT(0)
443 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
444 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
453 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
459 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
468 #define DWC3_DCTL_NYET_THRES_MASK (0xf << 20)
469 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
480 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
482 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
485 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
505 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
507 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
522 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
527 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
530 #define DWC3_DSTS_CONNECTSPD (7 << 0)
532 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
533 #define DWC3_DSTS_SUPERSPEED (4 << 0)
534 #define DWC3_DSTS_HIGHSPEED (0 << 0)
535 #define DWC3_DSTS_FULLSPEED BIT(0)
538 #define DWC3_DGCMD_SET_LMP 0x01
539 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
540 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
543 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
544 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
546 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
547 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
548 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
549 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
550 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
551 #define DWC3_DGCMD_DEV_NOTIFICATION 0x07
553 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
558 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
559 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
560 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
562 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
563 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
564 #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0)
570 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
571 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
577 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
578 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
579 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
580 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
581 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
582 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
584 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
586 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
587 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
588 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
590 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
592 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
598 #define DWC3_DEPCMD_TYPE_CONTROL 0
604 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
605 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
606 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
614 #define DWC3_OCFG_SRPCAP BIT(0)
624 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
647 #define DWC3_OEVT_ERROR BIT(0)
674 #define DWC3_OSTS_CONIDSTS BIT(0)
702 #define DWC3_EVENT_PENDING BIT(0)
709 #define DWC3_EP_FLAG_STALLED BIT(0)
760 #define DWC3_EP_ENABLED BIT(0)
808 DWC3_PHY_UNKNOWN = 0,
814 DWC3_EP0_UNKNOWN = 0,
821 EP0_UNCONNECTED = 0,
829 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
830 DWC3_LINK_STATE_U1 = 0x01,
831 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
832 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
833 DWC3_LINK_STATE_SS_DIS = 0x04,
834 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
835 DWC3_LINK_STATE_SS_INACT = 0x06,
836 DWC3_LINK_STATE_POLL = 0x07,
837 DWC3_LINK_STATE_RECOV = 0x08,
838 DWC3_LINK_STATE_HRESET = 0x09,
839 DWC3_LINK_STATE_CMPLY = 0x0a,
840 DWC3_LINK_STATE_LPBK = 0x0b,
841 DWC3_LINK_STATE_RESET = 0x0e,
842 DWC3_LINK_STATE_RESUME = 0x0f,
843 DWC3_LINK_STATE_MASK = 0x0f,
847 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
849 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
850 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
852 #define DWC3_TRBSTS_OK 0
858 #define DWC3_TRB_CTRL_HWO BIT(0)
862 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
865 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
866 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
868 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
919 #define DWC3_MODE(n) ((n) & 0x7)
923 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
926 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
927 #define DWC3_NUM_EPS_MASK (0x3f << 12)
934 #define DWC3_RAM0_DEPTH(n) (((n) & (0xffff0000)) >> 16)
937 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
969 #define DWC3_REQUEST_STATUS_QUEUED 0
1096 * 0 - utmi_sleep_n
1145 * 0 - -6dB de-emphasis
1157 * increments or 0 to disable.
1247 #define DWC3_IP 0x5533
1248 #define DWC31_IP 0x3331
1249 #define DWC32_IP 0x3332
1253 #define DWC3_REVISION_ANY 0x0
1254 #define DWC3_REVISION_173A 0x5533173a
1255 #define DWC3_REVISION_175A 0x5533175a
1256 #define DWC3_REVISION_180A 0x5533180a
1257 #define DWC3_REVISION_183A 0x5533183a
1258 #define DWC3_REVISION_185A 0x5533185a
1259 #define DWC3_REVISION_187A 0x5533187a
1260 #define DWC3_REVISION_188A 0x5533188a
1261 #define DWC3_REVISION_190A 0x5533190a
1262 #define DWC3_REVISION_194A 0x5533194a
1263 #define DWC3_REVISION_200A 0x5533200a
1264 #define DWC3_REVISION_202A 0x5533202a
1265 #define DWC3_REVISION_210A 0x5533210a
1266 #define DWC3_REVISION_220A 0x5533220a
1267 #define DWC3_REVISION_230A 0x5533230a
1268 #define DWC3_REVISION_240A 0x5533240a
1269 #define DWC3_REVISION_250A 0x5533250a
1270 #define DWC3_REVISION_260A 0x5533260a
1271 #define DWC3_REVISION_270A 0x5533270a
1272 #define DWC3_REVISION_280A 0x5533280a
1273 #define DWC3_REVISION_290A 0x5533290a
1274 #define DWC3_REVISION_300A 0x5533300a
1275 #define DWC3_REVISION_310A 0x5533310a
1276 #define DWC3_REVISION_320A 0x5533320a
1277 #define DWC3_REVISION_330A 0x5533330a
1279 #define DWC31_REVISION_ANY 0x0
1280 #define DWC31_REVISION_110A 0x3131302a
1281 #define DWC31_REVISION_120A 0x3132302a
1282 #define DWC31_REVISION_160A 0x3136302a
1283 #define DWC31_REVISION_170A 0x3137302a
1284 #define DWC31_REVISION_180A 0x3138302a
1285 #define DWC31_REVISION_190A 0x3139302a
1286 #define DWC31_REVISION_200A 0x3230302a
1288 #define DWC32_REVISION_ANY 0x0
1289 #define DWC32_REVISION_100A 0x3130302a
1293 #define DWC31_VERSIONTYPE_ANY 0x0
1294 #define DWC31_VERSIONTYPE_EA01 0x65613031
1295 #define DWC31_VERSIONTYPE_EA02 0x65613032
1296 #define DWC31_VERSIONTYPE_EA03 0x65613033
1297 #define DWC31_VERSIONTYPE_EA04 0x65613034
1298 #define DWC31_VERSIONTYPE_EA05 0x65613035
1299 #define DWC31_VERSIONTYPE_EA06 0x65613036
1399 #define INCRX_BURST_MODE 0
1412 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1413 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1414 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1415 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1416 #define DWC3_DEPEVT_STREAMEVT 0x06
1417 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1424 * 0x00 - Reserved
1425 * 0x01 - XferComplete
1426 * 0x02 - XferInProgress
1427 * 0x03 - XferNotReady
1428 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1429 * 0x05 - Reserved
1430 * 0x06 - StreamEvt
1431 * 0x07 - EPCmdCmplt
1449 #define DEPEVT_STATUS_BUSERR BIT(0)
1460 #define DEPEVT_STREAM_PRIME 0xfffe
1461 #define DEPEVT_STREAM_NOSTREAM 0x0
1475 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1481 * @device_event: indicates it's a device event. Should read as 0x00
1483 * 0 - DisconnEvt
1512 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1556 #define DWC3_HAS_PERIPHERAL BIT(0)
1616 { return 0; } in dwc3_host_init()
1635 { return 0; } in dwc3_gadget_init()
1639 { return 0; } in dwc3_gadget_set_test_mode()
1641 { return 0; } in dwc3_gadget_get_link_state()
1644 { return 0; } in dwc3_gadget_set_link_state()
1648 { return 0; } in dwc3_send_gadget_ep_cmd()
1651 { return 0; } in dwc3_send_gadget_generic_command()
1665 { return 0; } in dwc3_drd_init()
1685 return 0; in dwc3_gadget_suspend()
1690 return 0; in dwc3_gadget_resume()
1700 { return 0; } in dwc3_ulpi_init()