Lines Matching +full:send +full:- +full:flush +full:- +full:out +full:- +full:sequence
1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks ([email protected]). All rights
44 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
211 * - ...
256 * Incomplete Isochronous OUT Transfer Mask
260 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk)
264 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask
273 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk)
274 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
276 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
277 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
324 * This register interrupts the application for system-level events in the
343 * Power-Down and Clock Gating Programming Model" on
351 * Power-Down and Clock Gating Programming Model" on
371 * Channel-n Interrupt (HCINTn) register to determine the exact
391 * Incomplete Isochronous OUT Transfer (incompISOOUT)
393 * there is at least one isochronous OUT endpoint on which the
403 * @oepint: OUT Endpoints Interrupt (OEPInt)
405 * on one of the OUT endpoints of the core (in Device mode). The
407 * (DAINT) register to determine the exact number of the OUT
409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
424 * Indicates that an IN token has been received for a non-periodic
426 * top of the Non-Periodic Transmit FIFO and the IN endpoint
432 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
433 * The core sets this bit when it fails to write an isochronous OUT
436 * for the isochronous OUT endpoint.
456 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff)
457 * Indicates that the Set Global OUT NAK bit in the Device Control
460 * Global OUT NAK bit in the Device Control register
462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 * Indicates that the Set Global Non-Periodic IN NAK bit in the
467 * can be cleared by clearing the Clear Global Non-Periodic IN
470 * is sent out on the USB. The STALL bit takes precedence over
472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 * This interrupt is asserted when the Non-Periodic TxFIFO is
475 * one entry to be written to the Non-Periodic Transmit Request
477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
479 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
555 * Non-Periodic TxFIFO.
561 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
562 * This value is in terms of 32-bit words.
565 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
566 * This field contains the memory start address for Non-Periodic
579 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
581 * This read-only register contains the free space information for the
582 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
588 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
589 * Entry in the Non-Periodic Tx Request Queue that is currently
593 * - 2'b00: IN/OUT token
594 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
595 * - 2'b10: PING/CSPLIT token
596 * - 2'b11: Channel halt command
598 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
600 * Indicates the amount of free space available in the Non-
602 * and OUT requests in Host mode. Device mode has only IN
604 * * 8'h0: Non-Periodic Transmit Request Queue is full
609 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
610 * Indicates the amount of free space available in the Non-
612 * Values are in terms of 32-bit words.
613 * * 16'h0: Non-Periodic TxFIFO is full
648 * Flush bit. This field must not be changed until the core clears
649 * the TxFIFO Flush bit.
650 * * 5'h0: Non-Periodic TxFIFO flush
651 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
652 * TxFIFO flush in Host mode
653 * * 5'h2: Periodic TxFIFO 2 flush in Device mode
654 * - ...
655 * * 5'hF: Periodic TxFIFO 15 flush in Device mode
656 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
658 * @txfflsh: TxFIFO Flush (TxFFlsh)
667 * @rxfflsh: RxFIFO Flush (RxFFlsh)
668 * The application can flush the entire RxFIFO using this bit, but
677 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh)
678 * The application writes this bit to flush the IN Token Sequence
683 * the subsequent SOF sent out by the core will have a
686 * The application uses this bit to flush the control logic in the
700 * This is a self-clearing bit that the core clears after all
707 * - PCGCCTL.RstPdwnModule
708 * - PCGCCTL.GateHclk
709 * - PCGCCTL.PwrClmp
710 * - PCGCCTL.StopPPhyLPwrClkSelclk
711 * - GUSBCFG.PhyLPwrClkSel
712 * - GUSBCFG.DDRSel
713 * - GUSBCFG.PHYSel
714 * - GUSBCFG.FSIntf
715 * - GUSBCFG.ULPI_UTMI_Sel
716 * - GUSBCFG.PHYIf
717 * - HCFG.FSLSPclkSel
718 * - DCFG.DevSpd
727 * the core. This is a self-clearing bit and the core clears this
770 * This value is in terms of 32-bit words.
787 * pops the top data entry out of the RxFIFO.
832 * This register can be used to configure the core after power-on or a changing
833 * to Host mode or Device mode. It contains USB and USB-PHY related
844 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
863 * @hnpcap: HNP-Capable (HNPCap)
865 * @srpcap: SRP-Capable (SRPCap)
869 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
871 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
879 * field is added to the high-speed/full-speed interpacket timeout
884 * The USB standard timeout value for high-speed operation is
886 * value for full-speed operation is 16 to 18 (inclusive) bit
890 * High-speed operation:
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
893 * Full-speed operation:
894 * * One 30-MHz PHY clock = 0.4 bit times
895 * * One 60-MHz PHY clock = 0.2 bit times
896 * * One 48-MHz PHY clock = 0.25 bit times
926 * in the corresponding Host Channel-n Interrupt register.
970 * Host Channel-n Characteristics Register (HCCHAR)
998 * When the Split Enable bit of the Host Channel-n Split Control
1018 * @lspddev: Low-Speed Device (LSpdDev)
1020 * channel is communicating to a low-speed device.
1022 * Indicates whether the transaction is IN or OUT.
1023 * * 1'b0: OUT
1052 * This register configures the core after power-on. Do not make changes to this
1059 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1067 * * 1'b1: FS/LS-only, even if the connected device can support HS
1098 * Host Channel-n Interrupt Register (HCINT)
1100 * This register indicates the status of a channel with respect to USB- and
1101 * AHB-related events. The application must read this register when the Host
1105 * number for the Host Channel-n Interrupt register. The application must clear
1149 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1191 * Host Channel-n Split Control Register (HCSPLT)
1205 * This field is used to determine whether to send all, first,
1206 * middle, or last payloads with each OUT transaction.
1236 * Host Channel-n Transfer Size Register (HCTSIZ)
1252 * * 2'b11: MDATA (non-control)/SETUP (control)
1255 * number of packets to be transmitted (OUT) or received (IN).
1257 * transmission or reception of an OUT/IN packet. Once this count
1261 * For an OUT, this field is the number of data bytes the host will
1262 * send during the transfer.
1266 * size for IN transactions (periodic and non-periodic).
1291 * the interval between two consecutive SOFs (FS) or micro-
1292 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1350 * A single register holds USB port-related information such as USB reset,
1379 * PrtSpd must be zero (i.e. the interface must be in high-speed
1388 * * Bit [10]: Logic level of D-
1391 * When the application sets this bit, a reset sequence is
1393 * period and clear this bit after the reset sequence is
1425 * If the core detects a USB remote wakeup sequence, as
1446 * A port is enabled only by the core after a reset sequence,
1497 * This value is in terms of 32-bit words.
1514 * This read-only register contains the free space information for the Periodic
1526 * - 1'b0: send in even (micro)frame
1527 * - 1'b1: send in odd (micro)frame
1530 * - 2'b00: IN/OUT
1531 * - 2'b01: Zero-length packet
1532 * - 2'b10: CSPLIT
1533 * - 2'b11: Disable channel command
1540 * IN and OUT requests.
1550 * Values are in terms of 32-bit words
1585 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1591 * @p_x_on: Force USB-PHY on during suspend.
1592 * '1' USB-PHY XO block is powered-down during
1594 * '0' USB-PHY XO block is powered-up during
1600 * '0' The USB-PHY uses a 12MHz crystal as a clock source
1615 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1617 * '1' The USB-PHY XO Bias, Bandgap and PLL are
1698 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1705 * @lsbist: Low-Speed BIST Enable.
1706 * @fsbist: Full-Speed BIST Enable.
1707 * @hsbist: High-Speed BIST Enable.
1709 * Asserted at the end of the PHY BIST sequence.
1712 * the BIST sequence.
1713 * @tdata_out: PHY Test Data Out.
1717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1721 * - still provide 3.3V to USB_VDD33, and
1722 * - tie USB_REXT to 3.3V supply, and
1723 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1724 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1726 * with byte-counts between packets. When set to 0
1728 * 4-byte aligned address after adding byte-count.
1733 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1734 * This signal enables the pull-down resistance on
1735 * the D+ line. '1' pull down-resistance is connected
1738 * (downstream-facing port), dp_pulldown and
1741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1742 * This signal enables the pull-down resistance on
1743 * the D- line. '1' pull down-resistance is connected
1744 * to D-. '0' pull down resistance is not connected
1745 * to D-. When an A/B device is acting as a host
1746 * (downstream-facing port), dp_pulldown and
1752 * @tuning: Transmitter Tuning for High-Speed Operation.
1754 * times for high-speed operation.
1769 * when bit-stuffing is enabled.
1772 * when bit-stuffing is enabled.
1783 * @bist_enb: Built-In Self Test Enable.
1785 * @tdata_sel: Test Data Out Select.
1800 * free_clk, then re-enable them with an aligned
1805 * de-assertion.