Lines Matching +defs:val +defs:pixels
51 #define REG_FLD_MOD(idx, val, start, end) \ argument
251 static inline void dispc_write_reg(const u16 idx, u32 val) in dispc_write_reg()
268 enum mgr_reg_fields regfld, int val) { in mgr_fld_write()
720 u32 val; in dispc_ovl_set_pos() local
733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size() local
744 u32 val; in dispc_ovl_set_output_size() local
904 u32 val; in dispc_ovl_set_channel_out() local
966 u32 val; in dispc_ovl_get_channel_out() local
1076 u32 val; in dispc_ovl_set_vid_color_conv() local
1101 u32 val; in dispc_mgr_set_size() local
1360 u32 val; in dispc_ovl_set_fir() local
1381 u32 val; in dispc_ovl_set_vid_accu0() local
1395 u32 val; in dispc_ovl_set_vid_accu1() local
1410 u32 val; in dispc_ovl_set_vid_accu2_0() local
1419 u32 val; in dispc_ovl_set_vid_accu2_1() local
1794 static s32 pixinc(int pixels, u8 ps) in pixinc()
2101 u64 val, blank; in check_horiz_timing_omap3() local
3111 u32 mask, val; in _dispc_mgr_set_lcd_timings() local