Lines Matching full:u
13 #define TEGRA234_CLK_ACTMON 1U
15 #define TEGRA234_CLK_ADSP 2U
17 #define TEGRA234_CLK_ADSPNEON 3U
19 #define TEGRA234_CLK_AHUB 4U
21 #define TEGRA234_CLK_APB2APE 5U
23 #define TEGRA234_CLK_APE 6U
25 #define TEGRA234_CLK_AUD_MCLK 7U
27 #define TEGRA234_CLK_AXI_CBB 8U
29 #define TEGRA234_CLK_CAN1 9U
31 #define TEGRA234_CLK_CAN1_HOST 10U
33 #define TEGRA234_CLK_CAN2 11U
35 #define TEGRA234_CLK_CAN2_HOST 12U
37 #define TEGRA234_CLK_CLK_M 14U
39 #define TEGRA234_CLK_DMIC1 15U
41 #define TEGRA234_CLK_DMIC2 16U
43 #define TEGRA234_CLK_DMIC3 17U
45 #define TEGRA234_CLK_DMIC4 18U
47 #define TEGRA234_CLK_DPAUX 19U
49 #define TEGRA234_CLK_NVJPG1 20U
55 #define TEGRA234_CLK_ACLK 21U
57 #define TEGRA234_CLK_MSS_ENCRYPT 22U
59 #define TEGRA234_CLK_EQOS_RX_INPUT 23U
61 #define TEGRA234_CLK_AON_APB 25U
63 #define TEGRA234_CLK_AON_NIC 26U
65 #define TEGRA234_CLK_AON_CPU_NIC 27U
67 #define TEGRA234_CLK_PLLA1 28U
69 #define TEGRA234_CLK_DSPK1 29U
71 #define TEGRA234_CLK_DSPK2 30U
80 #define TEGRA234_CLK_EMC 31U
82 #define TEGRA234_CLK_EQOS_AXI 32U
84 #define TEGRA234_CLK_EQOS_PTP_REF 33U
86 #define TEGRA234_CLK_EQOS_RX 34U
88 #define TEGRA234_CLK_EQOS_TX 35U
90 #define TEGRA234_CLK_EXTPERIPH1 36U
92 #define TEGRA234_CLK_EXTPERIPH2 37U
94 #define TEGRA234_CLK_EXTPERIPH3 38U
96 #define TEGRA234_CLK_EXTPERIPH4 39U
98 #define TEGRA234_CLK_FUSE 40U
100 #define TEGRA234_CLK_GPC0CLK 41U
102 #define TEGRA234_CLK_GPU_PWR 42U
105 #define TEGRA234_CLK_HOST1X 46U
107 #define TEGRA234_CLK_XUSB_HS_HSICP 47U
109 #define TEGRA234_CLK_I2C1 48U
111 #define TEGRA234_CLK_I2C2 49U
113 #define TEGRA234_CLK_I2C3 50U
115 #define TEGRA234_CLK_I2C4 51U
117 #define TEGRA234_CLK_I2C6 52U
119 #define TEGRA234_CLK_I2C7 53U
121 #define TEGRA234_CLK_I2C8 54U
123 #define TEGRA234_CLK_I2C9 55U
125 #define TEGRA234_CLK_I2S1 56U
127 #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
129 #define TEGRA234_CLK_I2S2 58U
131 #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
133 #define TEGRA234_CLK_I2S3 60U
135 #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
137 #define TEGRA234_CLK_I2S4 62U
139 #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
141 #define TEGRA234_CLK_I2S5 64U
143 #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
145 #define TEGRA234_CLK_I2S6 66U
147 #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
149 #define TEGRA234_CLK_ISP 69U
151 #define TEGRA234_CLK_EQOS_RX_M 70U
153 #define TEGRA234_CLK_MAUD 71U
155 #define TEGRA234_CLK_MIPI_CAL 72U
157 #define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U
159 #define TEGRA234_CLK_MPHY_L0_RX_ANA 74U
161 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U
163 #define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U
165 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U
167 #define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U
169 #define TEGRA234_CLK_MPHY_L1_RX_ANA 79U
171 #define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U
173 #define TEGRA234_CLK_NVCSI 81U
175 #define TEGRA234_CLK_NVCSILP 82U
177 #define TEGRA234_CLK_NVDEC 83U
179 #define TEGRA234_CLK_HUB 84U
181 #define TEGRA234_CLK_DISP 85U
183 #define TEGRA234_CLK_NVDISPLAY_P0 86U
185 #define TEGRA234_CLK_NVDISPLAY_P1 87U
187 #define TEGRA234_CLK_DSC 88U
189 #define TEGRA234_CLK_NVENC 89U
191 #define TEGRA234_CLK_NVJPG 90U
193 #define TEGRA234_CLK_OSC 91U
195 #define TEGRA234_CLK_AON_TOUCH 92U
197 #define TEGRA234_CLK_PLLA 93U
199 #define TEGRA234_CLK_PLLAON 94U
201 #define TEGRA234_CLK_PLLE 100U
203 #define TEGRA234_CLK_PLLP 101U
205 #define TEGRA234_CLK_PLLP_OUT0 102U
207 #define TEGRA234_CLK_UTMIP_PLL 103U
209 #define TEGRA234_CLK_PLLA_OUT0 104U
211 #define TEGRA234_CLK_PWM1 105U
213 #define TEGRA234_CLK_PWM2 106U
215 #define TEGRA234_CLK_PWM3 107U
217 #define TEGRA234_CLK_PWM4 108U
219 #define TEGRA234_CLK_PWM5 109U
221 #define TEGRA234_CLK_PWM6 110U
223 #define TEGRA234_CLK_PWM7 111U
225 #define TEGRA234_CLK_PWM8 112U
227 #define TEGRA234_CLK_RCE_CPU_NIC 113U
229 #define TEGRA234_CLK_RCE_NIC 114U
231 #define TEGRA234_CLK_AON_I2C_SLOW 117U
233 #define TEGRA234_CLK_SCE_CPU_NIC 118U
235 #define TEGRA234_CLK_SCE_NIC 119U
237 #define TEGRA234_CLK_SDMMC1 120U
239 #define TEGRA234_CLK_UPHY_PLL3 121U
241 #define TEGRA234_CLK_SDMMC4 123U
243 #define TEGRA234_CLK_SE 124U
245 #define TEGRA234_CLK_SOR0_PLL_REF 125U
247 #define TEGRA234_CLK_SOR0_REF 126U
249 #define TEGRA234_CLK_SOR1_PLL_REF 127U
251 #define TEGRA234_CLK_PRE_SOR0_REF 128U
253 #define TEGRA234_CLK_SOR1_REF 129U
255 #define TEGRA234_CLK_PRE_SOR1_REF 130U
257 #define TEGRA234_CLK_SOR_SAFE 131U
259 #define TEGRA234_CLK_SOR0_DIV 132U
261 #define TEGRA234_CLK_DMIC5 134U
263 #define TEGRA234_CLK_SPI1 135U
265 #define TEGRA234_CLK_SPI2 136U
267 #define TEGRA234_CLK_SPI3 137U
269 #define TEGRA234_CLK_I2C_SLOW 138U
271 #define TEGRA234_CLK_SYNC_DMIC1 139U
273 #define TEGRA234_CLK_SYNC_DMIC2 140U
275 #define TEGRA234_CLK_SYNC_DMIC3 141U
277 #define TEGRA234_CLK_SYNC_DMIC4 142U
279 #define TEGRA234_CLK_SYNC_DSPK1 143U
281 #define TEGRA234_CLK_SYNC_DSPK2 144U
283 #define TEGRA234_CLK_SYNC_I2S1 145U
285 #define TEGRA234_CLK_SYNC_I2S2 146U
287 #define TEGRA234_CLK_SYNC_I2S3 147U
289 #define TEGRA234_CLK_SYNC_I2S4 148U
291 #define TEGRA234_CLK_SYNC_I2S5 149U
293 #define TEGRA234_CLK_SYNC_I2S6 150U
295 #define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U
297 #define TEGRA234_CLK_TACH0 152U
299 #define TEGRA234_CLK_TSEC 153U
301 #define TEGRA234_CLK_TSEC_PKA 154U
303 #define TEGRA234_CLK_UARTA 155U
305 #define TEGRA234_CLK_UARTB 156U
307 #define TEGRA234_CLK_UARTC 157U
309 #define TEGRA234_CLK_UARTD 158U
311 #define TEGRA234_CLK_UARTE 159U
313 #define TEGRA234_CLK_UARTF 160U
315 #define TEGRA234_CLK_PEX1_C6_CORE 161U
317 #define TEGRA234_CLK_UART_FST_MIPI_CAL 162U
319 #define TEGRA234_CLK_UFSDEV_REF 163U
321 #define TEGRA234_CLK_UFSHC 164U
323 #define TEGRA234_CLK_USB2_TRK 165U
325 #define TEGRA234_CLK_VI 166U
327 #define TEGRA234_CLK_VIC 167U
329 #define TEGRA234_CLK_CSITE 168U
331 #define TEGRA234_CLK_IST 169U
333 #define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U
335 #define TEGRA234_CLK_PEX2_C7_CORE 171U
337 #define TEGRA234_CLK_PEX2_C8_CORE 172U
339 #define TEGRA234_CLK_PEX2_C9_CORE 173U
341 #define TEGRA234_CLK_DLA0_FALCON 174U
343 #define TEGRA234_CLK_DLA0_CORE 175U
345 #define TEGRA234_CLK_DLA1_FALCON 176U
347 #define TEGRA234_CLK_DLA1_CORE 177U
349 #define TEGRA234_CLK_SOR0 178U
351 #define TEGRA234_CLK_SOR1 179U
353 #define TEGRA234_CLK_SOR_PAD_INPUT 180U
355 #define TEGRA234_CLK_PRE_SF0 181U
357 #define TEGRA234_CLK_SF0 182U
359 #define TEGRA234_CLK_SF1 183U
361 #define TEGRA234_CLK_DSI_PAD_INPUT 184U
363 #define TEGRA234_CLK_PEX2_C10_CORE 187U
365 #define TEGRA234_CLK_UARTI 188U
367 #define TEGRA234_CLK_UARTJ 189U
369 #define TEGRA234_CLK_UARTH 190U
371 #define TEGRA234_CLK_FUSE_SERIAL 191U
373 #define TEGRA234_CLK_QSPI0_2X_PM 192U
375 #define TEGRA234_CLK_QSPI1_2X_PM 193U
377 #define TEGRA234_CLK_QSPI0_PM 194U
379 #define TEGRA234_CLK_QSPI1_PM 195U
381 #define TEGRA234_CLK_VI_CONST 196U
383 #define TEGRA234_CLK_NAFLL_BPMP 197U
385 #define TEGRA234_CLK_NAFLL_SCE 198U
387 #define TEGRA234_CLK_NAFLL_NVDEC 199U
389 #define TEGRA234_CLK_NAFLL_NVJPG 200U
391 #define TEGRA234_CLK_NAFLL_TSEC 201U
393 #define TEGRA234_CLK_NAFLL_VI 203U
395 #define TEGRA234_CLK_NAFLL_SE 204U
397 #define TEGRA234_CLK_NAFLL_NVENC 205U
399 #define TEGRA234_CLK_NAFLL_ISP 206U
401 #define TEGRA234_CLK_NAFLL_VIC 207U
403 #define TEGRA234_CLK_NAFLL_AXICBB 209U
405 #define TEGRA234_CLK_NAFLL_NVJPG1 210U
407 #define TEGRA234_CLK_NAFLL_PVA0_CORE 211U
409 #define TEGRA234_CLK_NAFLL_PVA0_VPS 212U
411 #define TEGRA234_CLK_DBGAPB 213U
413 #define TEGRA234_CLK_NAFLL_RCE 214U
415 #define TEGRA234_CLK_LA 215U
417 #define TEGRA234_CLK_PLLP_OUT_JTAG 216U
419 #define TEGRA234_CLK_SDMMC4_AXICIF 217U
421 #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
423 #define TEGRA234_CLK_PEX0_C0_CORE 220U
425 #define TEGRA234_CLK_PEX0_C1_CORE 221U
427 #define TEGRA234_CLK_PEX0_C2_CORE 222U
429 #define TEGRA234_CLK_PEX0_C3_CORE 223U
431 #define TEGRA234_CLK_PEX0_C4_CORE 224U
433 #define TEGRA234_CLK_PEX1_C5_CORE 225U
435 #define TEGRA234_CLK_PEX0_C0_CORE_M 229U
437 #define TEGRA234_CLK_PEX0_C1_CORE_M 230U
439 #define TEGRA234_CLK_PEX0_C2_CORE_M 231U
441 #define TEGRA234_CLK_PEX0_C3_CORE_M 232U
443 #define TEGRA234_CLK_PEX0_C4_CORE_M 233U
445 #define TEGRA234_CLK_PEX1_C5_CORE_M 234U
447 #define TEGRA234_CLK_PEX1_C6_CORE_M 235U
449 #define TEGRA234_CLK_GPC1CLK 236U
451 #define TEGRA234_CLK_PLLC4 237U
453 #define TEGRA234_CLK_PLLC4_OUT1 239U
455 #define TEGRA234_CLK_PLLC4_OUT2 240U
457 #define TEGRA234_CLK_PLLC4_MUXED 241U
459 #define TEGRA234_CLK_PLLC4_VCO_DIV2 242U
461 #define TEGRA234_CLK_PLLNVHS 243U
463 #define TEGRA234_CLK_PEX2_C7_CORE_M 244U
465 #define TEGRA234_CLK_PEX2_C8_CORE_M 245U
467 #define TEGRA234_CLK_PEX2_C9_CORE_M 246U
469 #define TEGRA234_CLK_PEX2_C10_CORE_M 247U
471 #define TEGRA234_CLK_MGBE0_RX_INPUT 248U
473 #define TEGRA234_CLK_MGBE1_RX_INPUT 249U
475 #define TEGRA234_CLK_MGBE2_RX_INPUT 250U
477 #define TEGRA234_CLK_MGBE3_RX_INPUT 251U
479 #define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U
481 #define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U
483 #define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U
485 #define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U
487 #define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U
489 #define TEGRA234_CLK_NVHS_RX_BYP_REF 263U
491 #define TEGRA234_CLK_NVHS_PLL0_MGMT 264U
493 #define TEGRA234_CLK_XUSB_CORE_DEV 265U
495 #define TEGRA234_CLK_XUSB_CORE_MUX 266U
497 #define TEGRA234_CLK_XUSB_CORE_HOST 267U
499 #define TEGRA234_CLK_XUSB_CORE_SS 268U
501 #define TEGRA234_CLK_XUSB_FALCON 269U
503 #define TEGRA234_CLK_XUSB_FALCON_HOST 270U
505 #define TEGRA234_CLK_XUSB_FALCON_SS 271U
507 #define TEGRA234_CLK_XUSB_FS 272U
509 #define TEGRA234_CLK_XUSB_FS_HOST 273U
511 #define TEGRA234_CLK_XUSB_FS_DEV 274U
513 #define TEGRA234_CLK_XUSB_SS 275U
515 #define TEGRA234_CLK_XUSB_SS_DEV 276U
517 #define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U
519 #define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */
520 #define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U
522 #define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */
523 #define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U
525 #define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */
526 #define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U
528 #define TEGRA234_CLK_CAN1_CORE 284U
530 #define TEGRA234_CLK_CAN2_CORE 285U
532 #define TEGRA234_CLK_PLLA1_OUT1 286U
534 #define TEGRA234_CLK_PLLNVHS_HPS 287U
536 #define TEGRA234_CLK_PLLREFE_VCOOUT 288U
538 #define TEGRA234_CLK_CLK_32K 289U
540 #define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U
542 #define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U
544 #define TEGRA234_CLK_PLLNVCSI 294U
546 #define TEGRA234_CLK_PVA0_CPU_AXI 295U
548 #define TEGRA234_CLK_PVA0_VPS 297U
550 #define TEGRA234_CLK_NAFLL_DLA0_CORE 299U
552 #define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U
554 #define TEGRA234_CLK_NAFLL_DLA1_CORE 301U
556 #define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U
558 #define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U
560 #define TEGRA234_CLK_GPUSYS 304U
562 #define TEGRA234_CLK_I2C5 305U
564 #define TEGRA234_CLK_FR_SE 306U
566 #define TEGRA234_CLK_BPMP_CPU_NIC 307U
568 #define TEGRA234_CLK_BPMP_CPU 308U
570 #define TEGRA234_CLK_TSC 309U
572 #define TEGRA234_CLK_EMCSA_MPLL 310U
574 #define TEGRA234_CLK_EMCSB_MPLL 311U
576 #define TEGRA234_CLK_EMCSC_MPLL 312U
578 #define TEGRA234_CLK_EMCSD_MPLL 313U
580 #define TEGRA234_CLK_PLLC 314U
582 #define TEGRA234_CLK_PLLC2 315U
584 #define TEGRA234_CLK_TSC_REF 317U
586 #define TEGRA234_CLK_FUSE_BURN 318U
588 #define TEGRA234_CLK_PLLGBE 319U
590 #define TEGRA234_CLK_PLLGBE_HPS 320U
592 #define TEGRA234_CLK_EMCSA_EMC 321U
594 #define TEGRA234_CLK_EMCSB_EMC 322U
596 #define TEGRA234_CLK_EMCSC_EMC 323U
598 #define TEGRA234_CLK_EMCSD_EMC 324U
600 #define TEGRA234_CLK_PLLE_HPS 326U
602 #define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U
604 #define TEGRA234_CLK_PLLP_DIV17 328U
606 #define TEGRA234_CLK_SOC_THERM 329U
608 #define TEGRA234_CLK_TSENSE 330U
610 #define TEGRA234_CLK_FR_SEU1 331U
612 #define TEGRA234_CLK_NAFLL_OFA 333U
614 #define TEGRA234_CLK_OFA 334U
616 #define TEGRA234_CLK_NAFLL_SEU1 335U
618 #define TEGRA234_CLK_SEU1 336U
620 #define TEGRA234_CLK_SPI4 337U
622 #define TEGRA234_CLK_SPI5 338U
624 #define TEGRA234_CLK_DCE_CPU_NIC 339U
626 #define TEGRA234_CLK_DCE_NIC 340U
628 #define TEGRA234_CLK_NAFLL_DCE 341U
630 #define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U
632 #define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U
634 #define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U
636 #define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U
638 #define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U
640 #define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U
642 #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U
644 #define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U
646 #define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U
648 #define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U
650 #define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U
652 #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U
654 #define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U
656 #define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U
658 #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
660 #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
662 #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
664 #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
666 #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
668 #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
670 #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
672 #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
674 #define TEGRA234_CLK_TACH1 365U
676 #define TEGRA234_CLK_MGBES_APP 366U
678 #define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U
680 #define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U
682 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
684 #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
686 #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
688 #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
690 #define TEGRA234_CLK_MGBE0_RX_PCS 373U
692 #define TEGRA234_CLK_MGBE0_TX 374U
694 #define TEGRA234_CLK_MGBE0_TX_PCS 375U
696 #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
698 #define TEGRA234_CLK_MGBE0_MAC 377U
700 #define TEGRA234_CLK_MGBE0_MACSEC 378U
702 #define TEGRA234_CLK_MGBE0_EEE_PCS 379U
704 #define TEGRA234_CLK_MGBE0_APP 380U
706 #define TEGRA234_CLK_MGBE0_PTP_REF 381U
708 #define TEGRA234_CLK_MGBE1_RX_PCS 382U
710 #define TEGRA234_CLK_MGBE1_TX 383U
712 #define TEGRA234_CLK_MGBE1_TX_PCS 384U
714 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
716 #define TEGRA234_CLK_MGBE1_MAC 386U
718 #define TEGRA234_CLK_MGBE1_MACSEC 387U
720 #define TEGRA234_CLK_MGBE1_EEE_PCS 388U
722 #define TEGRA234_CLK_MGBE1_APP 389U
724 #define TEGRA234_CLK_MGBE1_PTP_REF 390U
726 #define TEGRA234_CLK_MGBE2_RX_PCS 391U
728 #define TEGRA234_CLK_MGBE2_TX 392U
730 #define TEGRA234_CLK_MGBE2_TX_PCS 393U
732 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
734 #define TEGRA234_CLK_MGBE2_MAC 395U
736 #define TEGRA234_CLK_MGBE2_MACSEC 396U
738 #define TEGRA234_CLK_MGBE2_EEE_PCS 397U
740 #define TEGRA234_CLK_MGBE2_APP 398U
742 #define TEGRA234_CLK_MGBE2_PTP_REF 399U
744 #define TEGRA234_CLK_MGBE3_RX_PCS 400U
746 #define TEGRA234_CLK_MGBE3_TX 401U
748 #define TEGRA234_CLK_MGBE3_TX_PCS 402U
750 #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
752 #define TEGRA234_CLK_MGBE3_MAC 404U
754 #define TEGRA234_CLK_MGBE3_MACSEC 405U
756 #define TEGRA234_CLK_MGBE3_EEE_PCS 406U
758 #define TEGRA234_CLK_MGBE3_APP 407U
760 #define TEGRA234_CLK_MGBE3_PTP_REF 408U
762 #define TEGRA234_CLK_GBE_RX_BYP_REF 409U
764 #define TEGRA234_CLK_GBE_PLL0_MGMT 410U
766 #define TEGRA234_CLK_GBE_PLL1_MGMT 411U
768 #define TEGRA234_CLK_GBE_PLL2_MGMT 412U
770 #define TEGRA234_CLK_EQOS_MACSEC_RX 413U
772 #define TEGRA234_CLK_EQOS_MACSEC_TX 414U
774 #define TEGRA234_CLK_EQOS_TX_DIVIDER 415U
776 #define TEGRA234_CLK_NVHS_PLL1_MGMT 416U
778 #define TEGRA234_CLK_EMCHUB 417U
780 #define TEGRA234_CLK_I2S7_SYNC_INPUT 418U
782 #define TEGRA234_CLK_SYNC_I2S7 419U
784 #define TEGRA234_CLK_I2S7 420U
786 #define TEGRA234_CLK_I2S7_PAD_M 421U
788 #define TEGRA234_CLK_I2S8_SYNC_INPUT 422U
790 #define TEGRA234_CLK_SYNC_I2S8 423U
792 #define TEGRA234_CLK_I2S8 424U
794 #define TEGRA234_CLK_I2S8_PAD_M 425U
796 #define TEGRA234_CLK_NAFLL_GPC0 426U
798 #define TEGRA234_CLK_NAFLL_GPC1 427U
800 #define TEGRA234_CLK_NAFLL_GPUSYS 428U
802 #define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */
803 #define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U
805 #define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */
806 #define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U
808 #define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */
809 #define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U
811 #define TEGRA234_CLK_SCE_CPU 432U
813 #define TEGRA234_CLK_RCE_CPU 433U
815 #define TEGRA234_CLK_DCE_CPU 434U
817 #define TEGRA234_CLK_DSIPLL_VCO 435U
819 #define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U
821 #define TEGRA234_CLK_DSIPLL_CLKOUTA 437U
823 #define TEGRA234_CLK_SPPLL0_VCO 438U
825 #define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U
827 #define TEGRA234_CLK_SPPLL0_CLKOUTA 440U
829 #define TEGRA234_CLK_SPPLL0_CLKOUTB 441U
831 #define TEGRA234_CLK_SPPLL0_DIV10 442U
833 #define TEGRA234_CLK_SPPLL0_DIV25 443U
835 #define TEGRA234_CLK_SPPLL0_DIV27PN 444U
837 #define TEGRA234_CLK_SPPLL1_VCO 445U
839 #define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U
841 #define TEGRA234_CLK_SPPLL1_DIV27PN 447U
843 #define TEGRA234_CLK_VPLL0_REF 448U
845 #define TEGRA234_CLK_VPLL0 449U
847 #define TEGRA234_CLK_VPLL1 450U
849 #define TEGRA234_CLK_NVDISPLAY_P0_REF 451U
851 #define TEGRA234_CLK_RG0 452U
853 #define TEGRA234_CLK_RG1 453U
855 #define TEGRA234_CLK_DISPPLL 454U
857 #define TEGRA234_CLK_DISPHUBPLL 455U
859 #define TEGRA234_CLK_DSI_LP 456U
861 #define TEGRA234_CLK_AZA_2XBIT 457U
863 #define TEGRA234_CLK_AZA_BIT 458U
865 #define TEGRA234_CLK_DSI_CORE 459U
867 #define TEGRA234_CLK_DSI_PIXEL 460U
869 #define TEGRA234_CLK_PRE_SOR0 461U
871 #define TEGRA234_CLK_PRE_SOR1 462U
873 #define TEGRA234_CLK_DP_LINK_REF 463U
875 #define TEGRA234_CLK_SOR_LINKA_INPUT 464U
877 #define TEGRA234_CLK_SOR_LINKA_AFIFO 465U
879 #define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U
881 #define TEGRA234_CLK_RG0_M 467U
883 #define TEGRA234_CLK_RG1_M 468U
885 #define TEGRA234_CLK_SOR0_M 469U
887 #define TEGRA234_CLK_SOR1_M 470U
889 #define TEGRA234_CLK_PLLHUB 471U
891 #define TEGRA234_CLK_MCHUB 472U
893 #define TEGRA234_CLK_EMCSA_MC 473U
895 #define TEGRA234_CLK_EMCSB_MC 474U
897 #define TEGRA234_CLK_EMCSC_MC 475U
899 #define TEGRA234_CLK_EMCSD_MC 476U