Lines Matching +full:enum +full:- +full:as +full:- +full:flags
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18 * typedef dma_cookie_t - an opaque DMA cookie
31 * enum dma_status - DMA transaction status
37 enum dma_status {
46 * enum dma_transaction_type - DMA transaction types/indexes
49 * automatically set as dma devices are registered.
51 enum dma_transaction_type {
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
79 enum dma_transfer_direction {
89 * ----------------------------
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96 * it is to be repeated and other per-transfer attributes.
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
153 enum dma_transfer_direction dir;
164 * struct dma_vec - DMA vector
174 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
176 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
178 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
181 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
182 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
183 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
186 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
198 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
204 enum dma_ctrl_flags {
218 * enum sum_check_bits - bit position of pq_check_flags
220 enum sum_check_bits {
226 * enum sum_check_flags - result of async_{xor,pq}_zero_sum operations
227 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
228 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
230 enum sum_check_flags {
237 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
243 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
244 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
249 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
255 * - DMA_DEV_TO_MEM:
263 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
267 * provided as helper functions.
274 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
282 * - DMA_DEV_TO_MEM:
292 enum dma_desc_metadata_mode {
299 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
310 * struct dma_router - DMA router structure
320 * struct dma_chan - devices supply DMA channels, clients use them
331 * @local: per-cpu pointer to a struct dma_chan_percpu
333 * @table_count: number of appearances in the mem-to-mem allocation table
336 * @private: private data for certain client-channel associations
365 * struct dma_chan_dev - relate sysfs device node to backing channel device
369 * @chan_dma_dev: The channel is using custom/different dma-mapping
380 * enum dma_slave_buswidth - defines bus width of the DMA slave
383 enum dma_slave_buswidth {
397 * struct dma_slave_config - dma slave channel runtime config
413 * @dst_addr_width: same as src_addr_width but for destination
415 * @src_maxburst: the maximum number of words (note: words, as in
420 * @dst_maxburst: same as src_maxburst but for destination target
426 * @dst_port_window_size: same as src_port_window_size but for the destination
435 * This struct is passed in as configuration data to a DMA engine
439 * will then be passed in as an argument to the function.
441 * The rationale for adding configuration information to this struct is as
448 enum dma_transfer_direction direction;
451 enum dma_slave_buswidth src_addr_width;
452 enum dma_slave_buswidth dst_addr_width;
463 * enum dma_residue_granularity - Granularity of the reported transfer residue
473 * the hardware supports scatter-gather and the segment descriptor has a field
482 enum dma_residue_granularity {
489 * struct dma_slave_caps - expose capabilities of a slave channel only
495 * Since the enum dma_transfer_direction is not defined as bit flag for
497 * should be checked by controller as well
498 * @min_burst: min burst capability per-transfer
499 * @max_burst: max burst capability per-transfer
521 enum dma_residue_granularity residue_granularity;
527 return dev_name(&chan->dev->device); in dma_chan_name()
531 * typedef dma_filter_fn - callback filter for dma_request_channel
537 * being returned. Where 'suitable' indicates a non-busy channel that
545 enum dmaengine_tx_result {
553 enum dmaengine_tx_result result;
588 * struct dma_async_tx_descriptor - async transaction descriptor
589 * ---dma generic offload fields---
590 * @cookie: tracking cookie for this transaction, set to -EBUSY if
592 * @flags: flags to augment operation preparation, control completion, and
609 * ---async_tx api specific fields---
616 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ member
625 enum dma_desc_metadata_mode desc_metadata_mode;
638 kref_get(&unmap->kref); in dma_set_unmap()
639 tx->unmap = unmap; in dma_set_unmap()
643 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
651 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) in dmaengine_get_unmap_data() argument
662 if (!tx->unmap) in dma_descriptor_unmap()
665 dmaengine_unmap_put(tx->unmap); in dma_descriptor_unmap()
666 tx->unmap = NULL; in dma_descriptor_unmap()
698 spin_lock_bh(&txd->lock); in txd_lock()
702 spin_unlock_bh(&txd->lock); in txd_unlock()
706 txd->next = next; in txd_chain()
707 next->parent = txd; in txd_chain()
711 txd->parent = NULL; in txd_clear_parent()
715 txd->next = NULL; in txd_clear_next()
719 return txd->parent; in txd_parent()
723 return txd->next; in txd_next()
728 * struct dma_tx_state - filled in to report the status of
745 * enum dmaengine_alignment - defines alignment of the DMA async tx
748 enum dmaengine_alignment {
761 * struct dma_slave_map - associates slave device and it's slave channel with
774 * struct dma_filter - information for slave device/channel to filter_fn/param
787 * struct dma_device - info on the entity supplying DMA services
794 * @cap_mask: one or more dma_capability flags
797 * @max_pq: maximum number of PQ sources and PQ-continue capability
811 * Since the enum dma_transfer_direction is not defined as bit flag for
813 * should be checked by controller as well
814 * @min_burst: min burst capability per-transfer
815 * @max_burst: max burst capability per-transfer
834 * @device_prep_peripheral_dma_vec: prepares a scatter-gather DMA transfer,
844 * with per-channel specific ones
877 enum dma_desc_metadata_mode desc_metadata_modes;
880 enum dmaengine_alignment copy_align;
881 enum dmaengine_alignment xor_align;
882 enum dmaengine_alignment pq_align;
883 enum dmaengine_alignment fill_align;
898 enum dma_residue_granularity residue_granularity;
906 size_t len, unsigned long flags);
909 unsigned int src_cnt, size_t len, unsigned long flags);
912 size_t len, enum sum_check_flags *result, unsigned long flags);
916 size_t len, unsigned long flags);
920 enum sum_check_flags *pqres, unsigned long flags);
923 unsigned long flags);
926 unsigned int nents, int value, unsigned long flags);
928 struct dma_chan *chan, unsigned long flags);
932 size_t nents, enum dma_transfer_direction direction,
933 unsigned long flags);
936 unsigned int sg_len, enum dma_transfer_direction direction,
937 unsigned long flags, void *context);
940 size_t period_len, enum dma_transfer_direction direction,
941 unsigned long flags);
944 unsigned long flags);
947 unsigned long flags);
956 enum dma_status (*device_tx_status)(struct dma_chan *chan,
969 if (chan->device->device_config) in dmaengine_slave_config()
970 return chan->device->device_config(chan, config); in dmaengine_slave_config()
972 return -ENOSYS; in dmaengine_slave_config()
975 static inline bool is_slave_direction(enum dma_transfer_direction direction) in is_slave_direction()
983 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_single() argument
990 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_single()
993 return chan->device->device_prep_slave_sg(chan, &sg, 1, in dmaengine_prep_slave_single()
994 dir, flags, NULL); in dmaengine_prep_slave_single()
998 * dmaengine_prep_peripheral_dma_vec() - Prepare a DMA scatter-gather descriptor
1003 * @flags: DMA engine flags
1007 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_peripheral_dma_vec() argument
1009 if (!chan || !chan->device || !chan->device->device_prep_peripheral_dma_vec) in dmaengine_prep_peripheral_dma_vec()
1012 return chan->device->device_prep_peripheral_dma_vec(chan, vecs, nents, in dmaengine_prep_peripheral_dma_vec()
1013 dir, flags); in dmaengine_prep_peripheral_dma_vec()
1018 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_sg() argument
1020 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_sg()
1023 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_slave_sg()
1024 dir, flags, NULL); in dmaengine_prep_slave_sg()
1031 enum dma_transfer_direction dir, unsigned long flags, in dmaengine_prep_rio_sg() argument
1034 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_rio_sg()
1037 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_rio_sg()
1038 dir, flags, rio_ext); in dmaengine_prep_rio_sg()
1044 size_t period_len, enum dma_transfer_direction dir, in dmaengine_prep_dma_cyclic()
1045 unsigned long flags) in dmaengine_prep_dma_cyclic() argument
1047 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) in dmaengine_prep_dma_cyclic()
1050 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, in dmaengine_prep_dma_cyclic()
1051 period_len, dir, flags); in dmaengine_prep_dma_cyclic()
1056 unsigned long flags) in dmaengine_prep_interleaved_dma() argument
1058 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) in dmaengine_prep_interleaved_dma()
1060 if (flags & DMA_PREP_REPEAT && in dmaengine_prep_interleaved_dma()
1061 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits)) in dmaengine_prep_interleaved_dma()
1064 return chan->device->device_prep_interleaved_dma(chan, xt, flags); in dmaengine_prep_interleaved_dma()
1068 * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1071 * @value: Treated as a single byte value that fills the destination buffer
1073 * @flags: DMA engine flags
1077 unsigned long flags) in dmaengine_prep_dma_memset() argument
1079 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) in dmaengine_prep_dma_memset()
1082 return chan->device->device_prep_dma_memset(chan, dest, value, in dmaengine_prep_dma_memset()
1083 len, flags); in dmaengine_prep_dma_memset()
1088 size_t len, unsigned long flags) in dmaengine_prep_dma_memcpy() argument
1090 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) in dmaengine_prep_dma_memcpy()
1093 return chan->device->device_prep_dma_memcpy(chan, dest, src, in dmaengine_prep_dma_memcpy()
1094 len, flags); in dmaengine_prep_dma_memcpy()
1098 enum dma_desc_metadata_mode mode) in dmaengine_is_metadata_mode_supported()
1103 return !!(chan->device->desc_metadata_modes & mode); in dmaengine_is_metadata_mode_supported()
1117 return -EINVAL; in dmaengine_desc_attach_metadata()
1128 return -EINVAL; in dmaengine_desc_set_metadata_len()
1133 * dmaengine_terminate_all() - Terminate all active DMA transfers
1141 if (chan->device->device_terminate_all) in dmaengine_terminate_all()
1142 return chan->device->device_terminate_all(chan); in dmaengine_terminate_all()
1144 return -ENOSYS; in dmaengine_terminate_all()
1148 * dmaengine_terminate_async() - Terminate all active DMA transfers
1162 * This function can be called from atomic context as well as from within a
1170 if (chan->device->device_terminate_all) in dmaengine_terminate_async()
1171 return chan->device->device_terminate_all(chan); in dmaengine_terminate_async()
1173 return -EINVAL; in dmaengine_terminate_async()
1177 * dmaengine_synchronize() - Synchronize DMA channel termination
1190 * This function must only be called from non-atomic context and must not be
1198 if (chan->device->device_synchronize) in dmaengine_synchronize()
1199 chan->device->device_synchronize(chan); in dmaengine_synchronize()
1203 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1212 * This function must only be called from non-atomic context and must not be
1231 if (chan->device->device_pause) in dmaengine_pause()
1232 return chan->device->device_pause(chan); in dmaengine_pause()
1234 return -ENOSYS; in dmaengine_pause()
1239 if (chan->device->device_resume) in dmaengine_resume()
1240 return chan->device->device_resume(chan); in dmaengine_resume()
1242 return -ENOSYS; in dmaengine_resume()
1245 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, in dmaengine_tx_status()
1248 return chan->device->device_tx_status(chan, cookie, state); in dmaengine_tx_status()
1253 return desc->tx_submit(desc); in dmaengine_submit()
1256 static inline bool dmaengine_check_align(enum dmaengine_alignment align, in dmaengine_check_align()
1259 return !(((1 << align) - 1) & (off1 | off2 | len)); in dmaengine_check_align()
1265 return dmaengine_check_align(dev->copy_align, off1, off2, len); in is_dma_copy_aligned()
1271 return dmaengine_check_align(dev->xor_align, off1, off2, len); in is_dma_xor_aligned()
1277 return dmaengine_check_align(dev->pq_align, off1, off2, len); in is_dma_pq_aligned()
1283 return dmaengine_check_align(dev->fill_align, off1, off2, len); in is_dma_fill_aligned()
1289 dma->max_pq = maxpq; in dma_set_maxpq()
1291 dma->max_pq |= DMA_HAS_PQ_CONTINUE; in dma_set_maxpq()
1294 static inline bool dmaf_continue(enum dma_ctrl_flags flags) in dmaf_continue() argument
1296 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; in dmaf_continue()
1299 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) in dmaf_p_disabled_continue() argument
1301 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; in dmaf_p_disabled_continue()
1303 return (flags & mask) == mask; in dmaf_p_disabled_continue()
1308 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; in dma_dev_has_pq_continue()
1313 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; in dma_dev_to_maxpq()
1316 /* dma_maxpq - reduce maxpq in the face of continued operations
1317 * @dma - dma device with PQ capability
1318 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1322 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1329 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) in dma_maxpq() argument
1331 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) in dma_maxpq()
1333 if (dmaf_p_disabled_continue(flags)) in dma_maxpq()
1334 return dma_dev_to_maxpq(dma) - 1; in dma_maxpq()
1335 if (dmaf_continue(flags)) in dma_maxpq()
1336 return dma_dev_to_maxpq(dma) - 3; in dma_maxpq()
1356 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, in dmaengine_get_dst_icg()
1357 chunk->icg, chunk->dst_icg); in dmaengine_get_dst_icg()
1363 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, in dmaengine_get_src_icg()
1364 chunk->icg, chunk->src_icg); in dmaengine_get_src_icg()
1367 /* --- public DMA engine API --- */
1397 async_dma_find_channel(enum dma_transaction_type type) in async_dma_find_channel()
1407 tx->flags |= DMA_CTRL_ACK; in async_tx_ack()
1412 tx->flags &= ~DMA_CTRL_ACK; in async_tx_clear_ack()
1417 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; in async_tx_test_ack()
1422 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_set()
1424 set_bit(tx_type, dstp->bits); in __dma_cap_set()
1429 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_clear()
1431 clear_bit(tx_type, dstp->bits); in __dma_cap_clear()
1437 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); in __dma_cap_zero()
1442 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) in __dma_has_cap()
1444 return test_bit(tx_type, srcp->bits); in __dma_has_cap()
1451 * dma_async_issue_pending - flush pending transactions to HW
1459 chan->device->device_issue_pending(chan); in dma_async_issue_pending()
1463 * dma_async_is_tx_complete - poll for transaction completion
1471 * the status of multiple cookies without re-checking hardware state.
1473 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, in dma_async_is_tx_complete()
1477 enum dma_status status; in dma_async_is_tx_complete()
1479 status = chan->device->device_tx_status(chan, cookie, &state); in dma_async_is_tx_complete()
1488 * dma_async_is_complete - test a cookie against chan state
1496 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, in dma_async_is_complete()
1515 st->last = last; in dma_set_tx_state()
1516 st->used = used; in dma_set_tx_state()
1517 st->residue = residue; in dma_set_tx_state()
1521 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1522 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1523 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1535 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) in dma_find_channel()
1539 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) in dma_sync_wait()
1543 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) in dma_wait_for_async_tx()
1560 return ERR_PTR(-ENODEV); in dma_request_chan()
1565 return ERR_PTR(-ENODEV); in dma_request_chan_by_mask()
1573 return -ENXIO; in dma_get_slave_caps()
1582 ret = dma_get_slave_caps(tx->chan, &caps); in dmaengine_desc_set_reuse()
1587 return -EPERM; in dmaengine_desc_set_reuse()
1589 tx->flags |= DMA_CTRL_REUSE; in dmaengine_desc_set_reuse()
1595 tx->flags &= ~DMA_CTRL_REUSE; in dmaengine_desc_clear_reuse()
1600 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; in dmaengine_desc_test_reuse()
1607 return -EPERM; in dmaengine_desc_free()
1609 return desc->desc_free(desc); in dmaengine_desc_free()
1612 /* --- DMA device --- */
1653 dmaengine_get_direction_text(enum dma_transfer_direction dir) in dmaengine_get_direction_text()
1671 if (chan->dev->chan_dma_dev) in dmaengine_get_dma_device()
1672 return &chan->dev->device; in dmaengine_get_dma_device()
1674 return chan->device->dev; in dmaengine_get_dma_device()