1285 #define MLX5_CAP_GEN(mdev, cap) \  argument
1288 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1291 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1294 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1297 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1300 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1303 #define MLX5_CAP_ETH(mdev, cap) \  argument
1307 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1311 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1314 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1317 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1320 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1323 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1326 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1329 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1332 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1335 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1338 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1341 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1344 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1347 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1351 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1354 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1357 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1360 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1363 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1366 #define MLX5_CAP_ESW(mdev, cap) \  argument
1370 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1374 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1378 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1382 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1386 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1389 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1392 #define MLX5_CAP_ODP(mdev, cap)\  argument
1395 #define MLX5_CAP_ODP_SCHEME(mdev, cap)                                \  argument
1403 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1406 #define MLX5_CAP_QOS(mdev, cap)\  argument
1409 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1439 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1442 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1445 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1448 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1451 #define MLX5_CAP_TLS(mdev, cap) \  argument
1454 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1457 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1461 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1465 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1468 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1471 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1474 #define MLX5_CAP_SHAMPO(mdev, cap) \  argument