Lines Matching +full:cs +full:- +full:to +full:- +full:clk

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 	/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 	/* ADV signal timings corresponding to GPMC_CONFIG3 */
47 	/* WE signals timings corresponding to GPMC_CONFIG4 */
51 	/* OE signals timings corresponding to GPMC_CONFIG4 */
57 	/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
59 	u32 access;		/* Start-cycle to first data valid delay */
78 	u32 t_ceasu;	/* address setup to CS valid */
79 	u32 t_avdasu;	/* address setup to ADV valid */
80 	/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
84 	 * variations of t_avdp as it is possible to have one
90 	u32 t_oeasu;	/* address setup to OE valid */
94 	u32 t_ce;	/* access time from CS asertion */
96 	u32 t_cez_r;	/* read CS deassertion to high Z */
97 	u32 t_cez_w;	/* write CS deassertion to high Z */
98 	u32 t_oez;	/* OE deassertion to high Z */
99 	u32 t_weasu;	/* address setup to WE valid */
104 	u32 clk;  member
105 	u32 t_bacc;	/* burst access valid clock to output delay */
106 	u32 t_ces;	/* CS setup time to clk */
107 	u32 t_avds;	/* ADV setup time to clk */
108 	u32 t_avdh;	/* ADV hold time from clk */
109 	u32 t_ach;	/* address hold time from clk */
110 	u32 t_rdyo;	/* clk to ready valid */
113 	u32 t_ce_avd;	/* CS on to ADV on delay */
134 #define GPMC_DEVWIDTH_8BIT		1	/* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT		2	/* 16-bit device width */
136 #define GPMC_MUX_AAD			1	/* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD			2	/* Addr-Data multiplex */
158 	u32 wait_pin;		/* wait-pin to be used */
165 	bool is_nand;			/* device within this CS is NAND */
169 	struct platform_device *pdev;	/* device within this CS region */
174 	struct gpmc_omap_cs_data cs[GPMC_CS_NUM];  member