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1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
31 /* Minimum clock period for synchronous mode (in picoseconds) */
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
80 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
112 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
115 /* XXX: check the possibility of combining
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
148 bool burst_read; /* enables read page/burst mode */
149 bool burst_write; /* enables write page/burst mode */
158 u32 wait_pin; /* wait-pin to be used */