160  * Different engines serve different roles, and there may be more than one
163  * on a certain subset of engines, or for providing information about that
170 	 * Render engines support instructions used for 3D, Compute (GPGPU),
181 	 * Copy engines (also referred to as "blitters") support instructions
184 	 * Copy engines can perform pre-defined logical or bitwise operations
192 	 * Video engines (also referred to as "bit stream decode" (BSD) or
201 	 * Video enhancement engines (also referred to as "vebox") support
209 	 * Compute engines support a subset of the instructions available
210 	 * on render engines:  compute engines support Compute (GPGPU) and
728  * value reports the support of context isolation for individual engines by
1284  * clients or engines (i.e. suballocating objects), the implicit tracking
1609 	 * conditions which prevent the report of which engines are busy from
1611 	 * object is idle, the result of the ioctl, that all engines are idle,
1624 	 * The high word (bits 16:31) are a bitmask of which engines classes
1625 	 * are currently reading from the object. Multiple engines may be
1631 	 * Some hardware may have parallel execution engines, e.g. multiple
1632 	 * media engines, which are mapped to the same class identifier and so
1637 	 * the object is idle or busy. The report of which engines are busy
1706 	 * Special GPU caching mode which is coherent with the scanout engines.
2052  * Bind this context to operate on this subset of available engines. Henceforth,
2054  * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
2062  * Setting the number of engines bound to the context to 0, by passing a zero
2192  * Not all GPUs or engines support this functionality in which case an error
2244  * physical engines, submit a batch buffer, and let the driver execute it on any
2248  * class engine, like for example GT3+ Skylake parts with their two VCS engines.
2250  * For instance userspace can enumerate all engines of a certain class using the
2266  * 		.engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
2269  * 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
2270  * 		.engines = { { I915_ENGINE_CLASS_INVALID,
2280  * 			.value = to_user_pointer(&engines),
2281  * 			.size = sizeof(engines),
2306  * Enable load balancing across this set of engines.
2309  * used will proxy the execbuffer request onto one of the set of engines
2312  * The set of engines must be compatible (e.g. the same HW class) as they
2316  * the backing engines (bypassing the load balancing proxy), the context must
2317  * be defined to use a single timeline for all engines.
2328 	struct i915_engine_class_instance engines[];  member
2337 	struct i915_engine_class_instance engines[N__]; \
2345  * All engines are equal, but some are more equal than others. Given
2347  * a request on a given subset of engines in parallel to a request on a
2348  * specific engine. We enable this selection of engines within a virtual
2360 	__u16 virtual_index; /* index of virtual engine in ctx->engines[] */
2366 	struct i915_engine_class_instance engines[];  member
2376 	struct i915_engine_class_instance engines[N__]; \
2416  *		     engines=CS[0],CS[1])
2424  *		     engines=CS[0],CS[2],CS[1],CS[3])
2430  *	This can be thought of as two virtual engines, each containing two
2431  *	engines thereby making a 2D array. However, there are bonds tying the
2443  *		     engines=CS[0],CS[1],CS[1],CS[3])
2488 	 * @engines: 2-d array of engine instances to configure parallel engine
2493 	struct i915_engine_class_instance engines[];  member
2505 	struct i915_engine_class_instance engines[N__]; \
2511  * Context engine map is a new way of addressing engines when submitting batch-
2515  * To use it created GEM contexts need to be configured with a list of engines
2527  * 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
2528  * 		.engines = { { I915_ENGINE_CLASS_RENDER, 0 },
2537  * 			.value = to_user_pointer(&engines),
2538  * 			.size = sizeof(engines),
2548  * 	// We have now created a GEM context with two engines in the map:
2549  * 	// Index 0 points to rcs0 while index 1 points to bcs0. Other engines
2568 	struct i915_engine_class_instance engines[];  member
2573 	struct i915_engine_class_instance engines[N__]; \
2868 	 * Multiple engines may be mapped to the same OA unit. The OA unit is
3273  * Engine discovery uAPI is a way of enumerating physical engines present in a
3279  * started to establish a pattern of having multiple engines of a same class,
3285  * Example for getting the list of engines:
3300  * 	// enough to hold our array of engines. The kernel will fill out the
3312  * 	// blob, which the kernel can then populate with info on all engines.
3320  * 		struct drm_i915_engine_info einfo = info->engines[i];
3328  * Each of the enumerated engines, apart from being defined by its class and
3332  * For instance video engines which support HEVC encoding will have the
3336  * of addressing engines when submitting batch buffers using contexts with
3373  * Engine info query enumerates all engines known to the driver by filling in
3383 	/** @engines: Marker for drm_i915_engine_info structures. */
3384 	struct drm_i915_engine_info engines[];  member