Lines Matching +full:4 +full:xx
30 * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
62 * PC16550D: 1 4 8 14 xx xx xx xx
63 * TI16C550A: 1 4 8 14 xx xx xx xx
64 * TI16C550C: 1 4 8 14 xx xx xx xx
65 * ST16C550: 1 4 8 14 xx xx xx xx
67 * NS16C552: 1 4 8 14 xx xx xx xx
69 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
72 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
85 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
90 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
103 #define UART_FCR_R_TRIG_MAX_STATE 4
128 #define UART_MCR 4 /* Out: Modem Control Register */
129 #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
130 #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
131 #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
186 #define UART_XON1 4 /* I/O: Xon character 1 */
192 * EFR[4]=1 MCR[6]=1, TI16C752
303 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
311 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
319 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
328 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */