Lines Matching +full:0 +full:x500
22 #define DMIC_INSTANCE 0x00
23 #define I2S_SP_INSTANCE 0x01
24 #define I2S_BT_INSTANCE 0x02
25 #define I2S_HS_INSTANCE 0x03
27 #define MEM_WINDOW_START 0x4080000
29 #define ACP_I2S_REG_START 0x1242400
30 #define ACP_I2S_REG_END 0x1242810
31 #define ACP3x_I2STDM_REG_START 0x1242400
32 #define ACP3x_I2STDM_REG_END 0x1242410
33 #define ACP3x_BT_TDM_REG_START 0x1242800
34 #define ACP3x_BT_TDM_REG_END 0x1242810
44 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
45 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
46 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
47 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
48 #define ACP_SRAM_PDM_PTE_OFFSET 0x400
49 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
50 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
51 #define PAGE_SIZE_4K_ENABLE 0x2
53 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
54 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
55 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
56 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
57 #define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
58 #define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
60 #define ACP7x_I2S_SP_TX_MEM_WINDOW_START 0x4000000
61 #define ACP7x_I2S_SP_RX_MEM_WINDOW_START 0x4200000
62 #define ACP7x_I2S_BT_TX_MEM_WINDOW_START 0x4400000
63 #define ACP7x_I2S_BT_RX_MEM_WINDOW_START 0x4600000
64 #define ACP7x_I2S_HS_TX_MEM_WINDOW_START 0x4800000
65 #define ACP7x_I2S_HS_RX_MEM_WINDOW_START 0x4A00000
66 #define ACP7x_DMIC_MEM_WINDOW_START 0x4C00000
68 #define SP_PB_FIFO_ADDR_OFFSET 0x500
69 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
70 #define BT_PB_FIFO_ADDR_OFFSET 0x900
71 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
72 #define HS_PB_FIFO_ADDR_OFFSET 0xD00
73 #define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
85 #define FIFO_SIZE 0x100
86 #define DMA_SIZE 0x40
87 #define FRM_LEN 0x100
89 #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
94 #define TDM_DISABLE 0
96 #define SLOT_WIDTH_8 0x8
97 #define SLOT_WIDTH_16 0x10
98 #define SLOT_WIDTH_24 0x18
99 #define SLOT_WIDTH_32 0x20
101 #define ACP6X_PGFSM_CONTROL 0x1024
102 #define ACP6X_PGFSM_STATUS 0x1028
110 #define ACP_ZSC_DSP_CTRL 0x0001014
111 #define ACP_ZSC_STS 0x0001018
112 #define ACP_SOFT_RST_DONE_MASK 0x00010001
114 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff
115 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
116 #define ACP_PGFSM_STATUS_MASK 0x03
117 #define ACP_POWERED_ON 0x00
118 #define ACP_POWER_ON_IN_PROGRESS 0x01
119 #define ACP_POWERED_OFF 0x02
120 #define ACP_POWER_OFF_IN_PROGRESS 0x03
122 #define ACP_ERROR_MASK 0x20000000
123 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
129 #define PDM_DMA_STAT 0x10
130 #define PDM_DMA_INTR_MASK 0x10000
131 #define PDM_DEC_64 0x2
132 #define PDM_CLK_FREQ_MASK 0x07
133 #define PDM_MISC_CTRL_MASK 0x10
134 #define PDM_ENABLE 0x01
135 #define PDM_DISABLE 0x00
136 #define DMA_EN_MASK 0x02
139 #define ACP_REGION2_OFFSET 0x02000000
207 ACP_CONFIG_0 = 0,
260 u64 byte_count = 0, low = 0, high = 0; in acp_get_byte_count()