Lines Matching +full:0 +full:x1801
16 #define CS42L84_CHIP_ID 0x42a84
18 #define CS42L84_DEVID 0x0000
19 #define CS42L84_REVID 0x73fe
20 #define CS42L84_FRZ_CTL 0x0006
21 #define CS42L84_FRZ_CTL_ENGAGE BIT(0)
23 #define CS42L84_TSRS_PLUG_INT_STATUS 0x0400
24 #define CS42L84_TSRS_PLUG_INT_MASK 0x0418
25 #define CS42L84_RS_PLUG_SHIFT 0
26 #define CS42L84_RS_PLUG BIT(0)
31 #define CS42L84_TSRS_PLUG_VAL_MASK GENMASK(3, 0)
32 #define CS42L84_PLL_LOCK_STATUS 0x040e // probably bit 0x10
37 #define CS42L84_UNPLUG 0
40 #define CS42L84_CCM_CTL1 0x0600
41 #define CS42L84_CCM_CTL1_MCLK_SRC GENMASK(1, 0)
42 #define CS42L84_CCM_CTL1_MCLK_SRC_RCO 0
47 #define CS42L84_CCM_CTL1_MCLK_F_12MHZ 0b00
48 #define CS42L84_CCM_CTL1_MCLK_F_24MHZ 0b01
49 #define CS42L84_CCM_CTL1_MCLK_F_12_288KHZ 0b10
50 #define CS42L84_CCM_CTL1_MCLK_F_24_576KHZ 0b11
55 #define CS42L84_CCM_SAMP_RATE 0x0601
62 #define CS42L84_CCM_CTL3 0x0602
64 #define CS42L84_CCM_CTL4 0x0603
65 #define CS42L84_CCM_CTL4_REFCLK_EN BIT(0)
67 #define CS42L84_CCM_ASP_CLK_CTRL 0x0608
69 #define CS42L84_PLL_CTL1 0x0800
70 #define CS42L84_PLL_CTL1_EN BIT(0)
72 #define CS42L84_PLL_DIV_FRAC0 0x0804
73 #define CS42L84_PLL_DIV_FRAC1 0x0805
74 #define CS42L84_PLL_DIV_FRAC2 0x0806
75 #define CS42L84_PLL_DIV_INT 0x0807
76 #define CS42L84_PLL_DIVOUT 0x0808
78 #define CS42L84_RING_SENSE_CTL 0x1282
82 #define CS42L84_RING_SENSE_CTL_RISETIME GENMASK(2, 0)
83 #define CS42L84_TIP_SENSE_CTL 0x1283
86 #define CS42L84_TIP_SENSE_CTL_RISETIME GENMASK(2, 0)
88 #define CS42L84_TSRS_PLUG_STATUS 0x1288
90 #define CS42L84_TIP_SENSE_CTL2 0x1473
92 #define CS42L84_TIP_SENSE_CTL2_MODE_DISABLED 0b00
93 #define CS42L84_TIP_SENSE_CTL2_MODE_DIG_INPUT 0b01
94 #define CS42L84_TIP_SENSE_CTL2_MODE_SHORT_DET 0b11
97 #define CS42L84_MISC_DET_CTL 0x1474
100 #define CS42L84_MISC_DET_CTL_PDN_MIC_LVL_DET BIT(0)
102 #define CS42L84_MIC_DET_CTL1 0x1475
103 #define CS42L84_MIC_DET_CTL1_HS_DET_LEVEL GENMASK(5, 0)
105 #define CS42L84_MIC_DET_CTL4 0x1477
108 #define CS42L84_HS_DET_STATUS2 0x147d
110 #define CS42L84_MSM_BLOCK_EN1 0x1800
111 #define CS42L84_MSM_BLOCK_EN2 0x1801
116 #define CS42L84_MSM_BLOCK_EN3 0x1802
119 #define CS42L84_HS_DET_CTL2 0x1811
123 #define CS42L84_HS_DET_CTL2_AUTO_TIME GENMASK(1, 0)
125 #define CS42L84_HS_SWITCH_CTL 0x1812
133 #define CS42L84_HS_SWITCH_CTL_GNDHS_HS4 BIT(0)
135 #define CS42L84_HS_CLAMP_DISABLE 0x1813
137 #define CS42L84_ADC_CTL1 0x2000
139 #define CS42L84_ADC_CTL1_PGA_GAIN_SHIFT 0
140 #define CS42L84_ADC_CTL4 0x2003
144 #define CS42L84_ADC_CTL4_HPF_EN_SHIFT 0
146 #define CS42L84_DAC_CTL1 0x3000
147 #define CS42L84_DAC_CTL1_UNMUTE BIT(0)
149 //#define CS42L84_DAC_CTL1_DACA_INV_SHIFT 0
150 #define CS42L84_DAC_CTL2 0x3001
152 #define CS42L84_DAC_CHA_VOL_LSB 0x3004
153 #define CS42L84_DAC_CHA_VOL_MSB 0x3005
154 #define CS42L84_DAC_CHB_VOL_LSB 0x3006
155 #define CS42L84_DAC_CHB_VOL_MSB 0x3007
156 #define CS42L84_HP_VOL_CTL 0x3020
158 #define CS42L84_HP_VOL_CTL_SOFT BIT(0)
160 #define CS42L84_SRC_ASP_RX_CH1 0b1101
161 #define CS42L84_SRC_ASP_RX_CH2 0b1110
163 #define CS42L84_BUS_ASP_TX_SRC 0x4000
164 #define CS42L84_BUS_ASP_TX_SRC_CH1_SHIFT 0
165 #define CS42L84_BUS_DAC_SRC 0x4001
166 #define CS42L84_BUS_DAC_SRC_DACA_SHIFT 0
169 #define CS42L84_ASP_CTL 0x5000
172 #define CS42L84_ASP_FSYNC_CTL2 0x5010
174 #define CS42L84_ASP_FSYNC_CTL3 0x5011
175 #define CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI GENMASK(4, 0)
176 #define CS42L84_ASP_DATA_CTL 0x5018
178 #define CS42L84_ASP_RX_EN 0x5020
179 #define CS42L84_ASP_RX_EN_CH1_SHIFT 0
181 #define CS42L84_ASP_TX_EN 0x5024
182 #define CS42L84_ASP_TX_EN_CH1_SHIFT 0
184 #define CS42L84_ASP_RX_CH1_CTL1 0x5028
185 #define CS42L84_ASP_RX_CH1_CTL2 0x5029
186 #define CS42L84_ASP_RX_CH1_WIDTH 0x502a
187 #define CS42L84_ASP_RX_CH2_CTL1 0x502c
188 #define CS42L84_ASP_RX_CH2_CTL2 0x502d
189 #define CS42L84_ASP_RX_CH2_WIDTH 0x502e
191 #define CS42L84_ASP_RX_CHx_CTL1_EDGE BIT(0)
193 #define CS42L84_ASP_RX_CHx_CTL2_SLOT_START_MSB GENMASK(2, 0)
195 #define CS42L84_ASP_TX_CH1_CTL1 0x5068
196 #define CS42L84_ASP_TX_CH1_CTL2 0x5069
197 #define CS42L84_ASP_TX_CH1_WIDTH 0x506a
198 #define CS42L84_ASP_TX_CH2_CTL1 0x506c
199 #define CS42L84_ASP_TX_CH2_CTL2 0x506d
200 #define CS42L84_ASP_TX_CH2_WIDTH 0x506e
202 #define CS42L84_DEBOUNCE_TIME_125MS 0b001
203 #define CS42L84_DEBOUNCE_TIME_500MS 0b011