Lines Matching +full:0 +full:xf1

14 #define CS4349_CHIPID		0x01	/* Device and Rev ID, Read Only */
15 #define CS4349_MODE		0x02	/* Mode Control */
16 #define CS4349_VMI		0x03	/* Volume, Mixing, Inversion Control */
17 #define CS4349_MUTE		0x04	/* Mute Control */
18 #define CS4349_VOLA		0x05	/* DAC Channel A Volume Control */
19 #define CS4349_VOLB		0x06	/* DAC Channel B Volume Control */
20 #define CS4349_RMPFLT		0x07	/* Ramp and Filter Control */
21 #define CS4349_MISC		0x08	/* Power Down,Freeze Control,Pop Stop*/
23 #define CS4349_I2C_INCR		0x80
27 #define CS4349_REVA		0xF0	/* Rev A */
28 #define CS4349_REVB		0xF1	/* Rev B */
29 #define CS4349_REVC2		0xFF	/* Rev C2 */
49 #define DIF_LEFT_JST		0x00
50 #define DIF_I2S			0x01
51 #define DIF_RGHT_JST16		0x02
52 #define DIF_RGHT_JST24		0x03
53 #define DIF_TDM0		0x04
54 #define DIF_TDM1		0x05
55 #define DIF_TDM2		0x06
56 #define DIF_TDM3		0x07
57 #define DIF_MASK		0x70
59 #define DEM_MASK		0x0C
60 #define NO_DEM			0x00
61 #define DEM_441			0x04
62 #define DEM_48K			0x08
63 #define DEM_32K			0x0C
64 #define FM_AUTO			0x00
65 #define FM_SNGL			0x01
66 #define FM_DBL			0x02
67 #define FM_QUAD			0x03
72 #define FM_MASK			0x03
84 #define ATAPI0			(1 << 0)
85 #define MUTEAB			0x00
86 #define MUTEA_RIGHTB		0x01
87 #define MUTEA_LEFTB		0x02
88 #define MUTEA_SUMLRDIV2B	0x03
89 #define RIGHTA_MUTEB		0x04
90 #define RIGHTA_RIGHTB		0x05
91 #define RIGHTA_LEFTB		0x06
92 #define RIGHTA_SUMLRDIV2B	0x07
93 #define LEFTA_MUTEB		0x08
94 #define LEFTA_RIGHTB		0x09	/* Default */
95 #define LEFTA_LEFTB		0x0A
96 #define LEFTA_SUMLRDIV2B	0x0B
97 #define SUMLRDIV2A_MUTEB	0x0C
98 #define SUMLRDIV2A_RIGHTB	0x0D
99 #define SUMLRDIV2A_LEFTB	0x0E
100 #define SUMLRDIV2_AB		0x0F
101 #define CHMIX_MASK		0x0F
108 #define MUTE_AB_MASK		0x18
116 #define IMMDT_CHNG		0x31
117 #define ZEROCRSS		0x71
118 #define SOFT_RMP		0xB1
119 #define SFTRMP_ZEROCRSS		0xF1
120 #define SR_ZC_MASK		0xC0