Lines Matching full:11
235 #define RT5651_SEL_DAC_L2 (0x1 << 11)
236 #define RT5651_IF2_DAC_L2 (0x1 << 11)
237 #define RT5651_IF1_DAC_L2 (0x0 << 11)
238 #define RT5651_SEL_DAC_L2_SFT 11
240 #define RT5651_IF2_DAC_R2 (0x1 << 11)
241 #define RT5651_IF1_DAC_R2 (0x0 << 11)
277 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
278 #define RT5651_STO1_ADC_2_SRC_SFT 11
279 #define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
280 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
295 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
296 #define RT5651_STO2_ADC_L2_SRC_SFT 11
297 #define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
298 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
329 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330 #define RT5651_DAC_L2_STO_L_VOL_SFT 11
355 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
356 #define RT5651_STO_DD_L2_VOL_SFT 11
383 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
384 #define RT5651_M_STO_R_DAC_R_SFT 11
414 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
415 #define RT5651_IF2_ADC_L_SEL_SFT 11
416 #define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
417 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
494 #define PT5631_PDM_CMD_EXE (0x1 << 11)
624 #define RT5651_M_BST1_SPM_L (0x1 << 11)
625 #define RT5651_M_BST1_SPM_L_SFT 11
632 #define RT5651_M_BST1_SPM_R (0x1 << 11)
633 #define RT5651_M_BST1_SPM_R_SFT 11
648 #define RT5651_M_BST1_MM (0x1 << 11)
649 #define RT5651_M_BST1_MM_SFT 11
722 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
723 #define RT5651_G_LOUTMIX_SFT 11
732 #define RT5651_PWR_DAC_R1 (0x1 << 11)
733 #define RT5651_PWR_DAC_R1_BIT 11
744 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
745 #define RT5651_PWR_DAC_STO1_F_BIT 11
760 #define RT5651_PWR_BG (0x1 << 11)
761 #define RT5651_PWR_BG_BIT 11
787 #define RT5651_PWR_MB1 (0x1 << 11)
788 #define RT5651_PWR_MB1_BIT 11
809 #define RT5651_PWR_RM_L (0x1 << 11)
810 #define RT5651_PWR_RM_L_BIT 11
819 #define RT5651_PWR_HV_L (0x1 << 11)
820 #define RT5651_PWR_HV_L_BIT 11
875 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
876 #define RT5651_I2S_BCLK_MS2_SFT 11
877 #define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
878 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
903 #define RT5651_DAHPF_EN (0x1 << 11)
904 #define RT5651_DAHPF_EN_SFT 11
996 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
997 #define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
998 #define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
999 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1091 #define RT5651_PLL_M_BP (0x1 << 11)
1092 #define RT5651_PLL_M_BP_SFT 11
1103 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1104 #define RT5651_ASRC2_REF_SFT 11
1105 #define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1106 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1125 #define RT5651_ADC_M_MASK (0x1 << 11)
1126 #define RT5651_ADC_M_SFT 11
1127 #define RT5651_ADC_M_NOR (0x0 << 11)
1128 #define RT5651_ADC_M_ASRC (0x1 << 11)
1240 #define RT5651_BPS_MASK (0x1 << 11)
1241 #define RT5651_BPS_SFT 11
1242 #define RT5651_BPS_DIS (0x0 << 11)
1243 #define RT5651_BPS_EN (0x1 << 11)
1284 #define RT5651_OSW_L_MASK (0x1 << 11)
1285 #define RT5651_OSW_L_SFT 11
1286 #define RT5651_OSW_L_DIS (0x0 << 11)
1287 #define RT5651_OSW_L_EN (0x1 << 11)
1313 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1314 #define RT5651_MIC1_OVCD_SFT 11
1315 #define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1316 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1334 #define RT5651_JD_PU (0x1 << 11)
1335 #define RT5651_JD_PU_SFT 11
1504 #define RT5651_JD_HP_MASK (0x1 << 11)
1505 #define RT5651_JD_HP_SFT 11
1506 #define RT5651_JD_HP_DIS (0x0 << 11)
1507 #define RT5651_JD_HP_EN (0x1 << 11)
1561 #define RT5651_JD_P_MASK (0x1 << 11)
1562 #define RT5651_JD_P_SFT 11
1563 #define RT5651_JD_P_NOR (0x0 << 11)
1564 #define RT5651_JD_P_INV (0x1 << 11)
1589 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1590 #define RT5651_MB1_OC_STKY_SFT 11
1591 #define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1592 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1612 #define RT5651_STA_GP7 (0x1 << 11)
1613 #define RT5651_STA_GP7_BIT 11
1680 #define RT5651_GP4_DR_MASK (0x1 << 11)
1681 #define RT5651_GP4_DR_SFT 11
1682 #define RT5651_GP4_DR_IN (0x0 << 11)
1683 #define RT5651_GP4_DR_OUT (0x1 << 11)
1842 #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1843 #define RT5651_3D_1F_MIX_SFT 11
1882 #define RT5651_SI_DAC_MASK (0x1 << 11)
1883 #define RT5651_SI_DAC_SFT 11
1884 #define RT5651_SI_DAC_AUTO (0x0 << 11)
1885 #define RT5651_SI_DAC_TEST (0x1 << 11)
1931 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1932 #define RT5651_ZCD_DIG_SFT 11
1933 #define RT5651_ZCD_DIG_DIS (0x0 << 11)
1934 #define RT5651_ZCD_DIG_EN (0x1 << 11)