Lines Matching +full:da830 +full:- +full:mcasp +full:- +full:audio
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-[email protected]>,
37 #include "edma-pcm.h"
38 #include "sdma-pcm.h"
39 #include "udma-pcm.h"
40 #include "davinci-mcasp.h"
71 struct davinci_mcasp *mcasp; member
86 /* Audio can not be enabled due to missing parameter(s) */
89 /* McASP specific data */
108 /* McASP FIFO related */
131 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_bits() argument
134 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
138 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_clr_bits() argument
141 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
145 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_mod_bits() argument
148 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
152 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_reg() argument
155 __raw_writel(val, mcasp->base + offset); in mcasp_set_reg()
158 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) in mcasp_get_reg() argument
160 return (u32)__raw_readl(mcasp->base + offset); in mcasp_get_reg()
163 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
167 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
170 /* loop count is to avoid the lock-up */ in mcasp_set_ctl_reg()
172 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
176 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
180 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) in mcasp_is_synchronous() argument
182 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); in mcasp_is_synchronous()
183 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); in mcasp_is_synchronous()
188 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) in mcasp_set_clk_pdir() argument
192 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { in mcasp_set_clk_pdir()
194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_clk_pdir()
196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_clk_pdir()
200 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) in mcasp_set_axr_pdir() argument
204 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { in mcasp_set_axr_pdir()
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_axr_pdir()
208 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_axr_pdir()
212 static void mcasp_start_rx(struct davinci_mcasp *mcasp) in mcasp_start_rx() argument
214 if (mcasp->rxnumevt) { /* enable FIFO */ in mcasp_start_rx()
215 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_start_rx()
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); in mcasp_start_rx()
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); in mcasp_start_rx()
229 if (mcasp_is_synchronous(mcasp)) { in mcasp_start_rx()
230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_rx()
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_rx()
232 mcasp_set_clk_pdir(mcasp, true); in mcasp_start_rx()
236 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_start_rx()
237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); in mcasp_start_rx()
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); in mcasp_start_rx()
241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); in mcasp_start_rx()
242 if (mcasp_is_synchronous(mcasp)) in mcasp_start_rx()
243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_rx()
246 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_start_rx()
247 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_start_rx()
250 static void mcasp_start_tx(struct davinci_mcasp *mcasp) in mcasp_start_tx() argument
254 if (mcasp->txnumevt) { /* enable FIFO */ in mcasp_start_tx()
255 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_start_tx()
257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
258 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_tx()
263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_tx()
264 mcasp_set_clk_pdir(mcasp, true); in mcasp_start_tx()
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_start_tx()
268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); in mcasp_start_tx()
272 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && in mcasp_start_tx()
276 mcasp_set_axr_pdir(mcasp, true); in mcasp_start_tx()
279 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); in mcasp_start_tx()
281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_tx()
284 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_start_tx()
285 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_start_tx()
288 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_start() argument
290 mcasp->streams++; in davinci_mcasp_start()
293 mcasp_start_tx(mcasp); in davinci_mcasp_start()
295 mcasp_start_rx(mcasp); in davinci_mcasp_start()
298 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) in mcasp_stop_rx() argument
301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_stop_rx()
302 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_stop_rx()
308 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { in mcasp_stop_rx()
309 mcasp_set_clk_pdir(mcasp, false); in mcasp_stop_rx()
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); in mcasp_stop_rx()
313 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); in mcasp_stop_rx()
314 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_rx()
316 if (mcasp->rxnumevt) { /* disable FIFO */ in mcasp_stop_rx()
317 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_stop_rx()
319 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_rx()
323 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) in mcasp_stop_tx() argument
328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_stop_tx()
329 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_stop_tx()
335 if (mcasp_is_synchronous(mcasp) && mcasp->streams) in mcasp_stop_tx()
338 mcasp_set_clk_pdir(mcasp, false); in mcasp_stop_tx()
341 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); in mcasp_stop_tx()
342 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_tx()
344 if (mcasp->txnumevt) { /* disable FIFO */ in mcasp_stop_tx()
345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_stop_tx()
347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_tx()
350 mcasp_set_axr_pdir(mcasp, false); in mcasp_stop_tx()
353 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_stop() argument
355 mcasp->streams--; in davinci_mcasp_stop()
358 mcasp_stop_tx(mcasp); in davinci_mcasp_stop()
360 mcasp_stop_rx(mcasp); in davinci_mcasp_stop()
365 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_tx_irq_handler() local
367 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
371 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); in davinci_mcasp_tx_irq_handler()
373 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); in davinci_mcasp_tx_irq_handler()
376 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
382 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", in davinci_mcasp_tx_irq_handler()
389 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); in davinci_mcasp_tx_irq_handler()
396 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_rx_irq_handler() local
398 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
402 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); in davinci_mcasp_rx_irq_handler()
404 dev_warn(mcasp->dev, "Receive buffer overflow\n"); in davinci_mcasp_rx_irq_handler()
407 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
413 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", in davinci_mcasp_rx_irq_handler()
420 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); in davinci_mcasp_rx_irq_handler()
427 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_common_irq_handler() local
430 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) in davinci_mcasp_common_irq_handler()
433 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) in davinci_mcasp_common_irq_handler()
442 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_set_dai_fmt() local
451 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_dai_fmt()
454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
467 /* configure a full-word SYNC pulse (LRCLK) */ in davinci_mcasp_set_dai_fmt()
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
477 /* configure a full-word SYNC pulse (LRCLK) */ in davinci_mcasp_set_dai_fmt()
478 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
484 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), in davinci_mcasp_set_dai_fmt()
490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), in davinci_mcasp_set_dai_fmt()
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
500 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
503 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
504 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
506 set_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
507 set_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
509 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
520 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
521 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
523 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
524 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
526 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
537 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
538 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
540 set_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
541 set_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
543 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
554 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
555 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
557 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
558 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
560 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
563 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
569 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
574 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
579 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
580 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
584 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
589 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
598 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
604 mcasp->dai_fmt = fmt; in davinci_mcasp_set_dai_fmt()
606 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_dai_fmt()
610 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, in __davinci_mcasp_set_clkdiv() argument
613 pm_runtime_get_sync(mcasp->dev); in __davinci_mcasp_set_clkdiv()
616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
617 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); in __davinci_mcasp_set_clkdiv()
618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
619 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); in __davinci_mcasp_set_clkdiv()
623 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
624 ACLKXDIV(div - 1), ACLKXDIV_MASK); in __davinci_mcasp_set_clkdiv()
625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
626 ACLKRDIV(div - 1), ACLKRDIV_MASK); in __davinci_mcasp_set_clkdiv()
628 mcasp->bclk_div = div; in __davinci_mcasp_set_clkdiv()
633 * BCLK/LRCLK ratio descries how many bit-clock cycles in __davinci_mcasp_set_clkdiv()
637 * of tdm-slots (for I2S - divided by 2). in __davinci_mcasp_set_clkdiv()
642 mcasp->slot_width = div / mcasp->tdm_slots; in __davinci_mcasp_set_clkdiv()
643 if (div % mcasp->tdm_slots) in __davinci_mcasp_set_clkdiv()
644 dev_warn(mcasp->dev, in __davinci_mcasp_set_clkdiv()
646 __func__, div, mcasp->tdm_slots); in __davinci_mcasp_set_clkdiv()
650 return -EINVAL; in __davinci_mcasp_set_clkdiv()
653 pm_runtime_put(mcasp->dev); in __davinci_mcasp_set_clkdiv()
660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_clkdiv() local
662 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); in davinci_mcasp_set_clkdiv()
668 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_sysclk() local
670 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_sysclk()
675 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in davinci_mcasp_set_sysclk()
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in davinci_mcasp_set_sysclk()
679 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
682 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in davinci_mcasp_set_sysclk()
684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in davinci_mcasp_set_sysclk()
686 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
689 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); in davinci_mcasp_set_sysclk()
694 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
696 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
700 * the same clock - coming via AUXCLK. in davinci_mcasp_set_sysclk()
702 mcasp->sysclk_freq = freq; in davinci_mcasp_set_sysclk()
704 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_sysclk()
709 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, in davinci_mcasp_ch_constraint() argument
712 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; in davinci_mcasp_ch_constraint()
713 unsigned int *list = (unsigned int *) cl->list; in davinci_mcasp_ch_constraint()
714 int slots = mcasp->tdm_slots; in davinci_mcasp_ch_constraint()
717 if (mcasp->tdm_mask[stream]) in davinci_mcasp_ch_constraint()
718 slots = hweight32(mcasp->tdm_mask[stream]); in davinci_mcasp_ch_constraint()
726 cl->count = count; in davinci_mcasp_ch_constraint()
731 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) in davinci_mcasp_set_ch_constraints() argument
735 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_set_ch_constraints()
736 if (mcasp->serial_dir[i] == TX_MODE) in davinci_mcasp_set_ch_constraints()
738 else if (mcasp->serial_dir[i] == RX_MODE) in davinci_mcasp_set_ch_constraints()
741 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, in davinci_mcasp_set_ch_constraints()
746 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, in davinci_mcasp_set_ch_constraints()
758 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_tdm_slot() local
760 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_set_tdm_slot()
763 dev_dbg(mcasp->dev, in davinci_mcasp_set_tdm_slot()
768 dev_err(mcasp->dev, in davinci_mcasp_set_tdm_slot()
771 return -EINVAL; in davinci_mcasp_set_tdm_slot()
776 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", in davinci_mcasp_set_tdm_slot()
778 return -EINVAL; in davinci_mcasp_set_tdm_slot()
781 mcasp->tdm_slots = slots; in davinci_mcasp_set_tdm_slot()
782 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; in davinci_mcasp_set_tdm_slot()
783 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; in davinci_mcasp_set_tdm_slot()
784 mcasp->slot_width = slot_width; in davinci_mcasp_set_tdm_slot()
786 return davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_set_tdm_slot()
789 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, in davinci_config_channel_size() argument
794 u32 mask = (1ULL << sample_width) - 1; in davinci_config_channel_size()
796 if (mcasp->slot_width) in davinci_config_channel_size()
797 slot_width = mcasp->slot_width; in davinci_config_channel_size()
798 else if (mcasp->max_format_width) in davinci_config_channel_size()
799 slot_width = mcasp->max_format_width; in davinci_config_channel_size()
809 * left aligned formats: rotate w/ (slot_width - sample_width) in davinci_config_channel_size()
811 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == in davinci_config_channel_size()
817 rx_rotate = (slot_width - sample_width) / 4; in davinci_config_channel_size()
820 /* mapping of the XSSZ bit-field as described in the datasheet */ in davinci_config_channel_size()
821 fmt = (slot_width >> 1) - 1; in davinci_config_channel_size()
823 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_config_channel_size()
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), in davinci_config_channel_size()
826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), in davinci_config_channel_size()
828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), in davinci_config_channel_size()
830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), in davinci_config_channel_size()
832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); in davinci_config_channel_size()
836 * 16 bit to 23-8 (TXROT=6, rotate 24 bits) in davinci_config_channel_size()
837 * 24 bit to 23-0 (TXROT=0, rotate 0 bits) in davinci_config_channel_size()
843 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), in davinci_config_channel_size()
845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15), in davinci_config_channel_size()
849 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); in davinci_config_channel_size()
854 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_common_hw_param() argument
857 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; in mcasp_common_hw_param()
861 u8 slots = mcasp->tdm_slots; in mcasp_common_hw_param()
867 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in mcasp_common_hw_param()
873 if (mcasp->version < MCASP_VERSION_3) in mcasp_common_hw_param()
874 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); in mcasp_common_hw_param()
877 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
878 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_common_hw_param()
881 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; in mcasp_common_hw_param()
883 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
884 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); in mcasp_common_hw_param()
886 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; in mcasp_common_hw_param()
890 for (i = 0; i < mcasp->num_serializer; i++) { in mcasp_common_hw_param()
891 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
892 mcasp->serial_dir[i]); in mcasp_common_hw_param()
893 if (mcasp->serial_dir[i] == TX_MODE && in mcasp_common_hw_param()
895 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
896 mcasp->dismod, DISMOD_MASK); in mcasp_common_hw_param()
897 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
899 } else if (mcasp->serial_dir[i] == RX_MODE && in mcasp_common_hw_param()
901 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
908 if (mcasp->serial_dir[i] != INACTIVE_MODE) in mcasp_common_hw_param()
909 mcasp_mod_bits(mcasp, in mcasp_common_hw_param()
911 mcasp->dismod, DISMOD_MASK); in mcasp_common_hw_param()
912 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
918 numevt = mcasp->txnumevt; in mcasp_common_hw_param()
919 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_common_hw_param()
922 numevt = mcasp->rxnumevt; in mcasp_common_hw_param()
923 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_common_hw_param()
927 dev_warn(mcasp->dev, "stream has more channels (%d) than are " in mcasp_common_hw_param()
928 "enabled in mcasp (%d)\n", channels, in mcasp_common_hw_param()
930 return -EINVAL; in mcasp_common_hw_param()
943 dma_data->maxburst = active_serializers; in mcasp_common_hw_param()
945 dma_data->maxburst = 0; in mcasp_common_hw_param()
952 dev_err(mcasp->dev, "Invalid combination of period words and " in mcasp_common_hw_param()
955 return -EINVAL; in mcasp_common_hw_param()
966 numevt -= active_serializers; in mcasp_common_hw_param()
970 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); in mcasp_common_hw_param()
971 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); in mcasp_common_hw_param()
976 dma_data->maxburst = numevt; in mcasp_common_hw_param()
979 mcasp->active_serializers[stream] = active_serializers; in mcasp_common_hw_param()
984 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_i2s_hw_param() argument
993 total_slots = mcasp->tdm_slots; in mcasp_i2s_hw_param()
1001 if (mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
1002 active_slots = hweight32(mcasp->tdm_mask[stream]); in mcasp_i2s_hw_param()
1007 if ((1 << i) & mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
1009 if (--active_slots <= 0) in mcasp_i2s_hw_param()
1024 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); in mcasp_i2s_hw_param()
1026 if (!mcasp->dat_port) in mcasp_i2s_hw_param()
1030 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); in mcasp_i2s_hw_param()
1031 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); in mcasp_i2s_hw_param()
1032 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
1035 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); in mcasp_i2s_hw_param()
1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); in mcasp_i2s_hw_param()
1037 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, in mcasp_i2s_hw_param()
1040 * If McASP is set to be TX/RX synchronous and the playback is in mcasp_i2s_hw_param()
1044 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) in mcasp_i2s_hw_param()
1045 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
1053 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, in mcasp_dit_hw_param() argument
1056 u8 *cs_bytes = (u8 *)&mcasp->iec958_status; in mcasp_dit_hw_param()
1058 if (!mcasp->dat_port) in mcasp_dit_hw_param()
1059 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); in mcasp_dit_hw_param()
1061 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); in mcasp_dit_hw_param()
1064 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); in mcasp_dit_hw_param()
1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF); in mcasp_dit_hw_param()
1069 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); in mcasp_dit_hw_param()
1072 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); in mcasp_dit_hw_param()
1074 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_dit_hw_param()
1107 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate); in mcasp_dit_hw_param()
1108 return -EINVAL; in mcasp_dit_hw_param()
1111 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status); in mcasp_dit_hw_param()
1112 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status); in mcasp_dit_hw_param()
1115 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); in mcasp_dit_hw_param()
1120 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, in davinci_mcasp_calc_clk_div() argument
1124 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); in davinci_mcasp_calc_clk_div()
1140 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", in davinci_mcasp_calc_clk_div()
1147 ((sysclk_freq / div) - bclk_freq) > in davinci_mcasp_calc_clk_div()
1148 (bclk_freq - (sysclk_freq / (div+1)))) { in davinci_mcasp_calc_clk_div()
1150 rem = rem - bclk_freq; in davinci_mcasp_calc_clk_div()
1154 (int)bclk_freq)) / div - 1000000; in davinci_mcasp_calc_clk_div()
1158 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", in davinci_mcasp_calc_clk_div()
1161 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); in davinci_mcasp_calc_clk_div()
1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, in davinci_mcasp_calc_clk_div()
1170 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) in davinci_mcasp_tx_delay() argument
1172 if (!mcasp->txnumevt) in davinci_mcasp_tx_delay()
1175 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); in davinci_mcasp_tx_delay()
1178 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) in davinci_mcasp_rx_delay() argument
1180 if (!mcasp->rxnumevt) in davinci_mcasp_rx_delay()
1183 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); in davinci_mcasp_rx_delay()
1190 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_delay() local
1193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in davinci_mcasp_delay()
1194 fifo_use = davinci_mcasp_tx_delay(mcasp); in davinci_mcasp_delay()
1196 fifo_use = davinci_mcasp_rx_delay(mcasp); in davinci_mcasp_delay()
1203 return fifo_use / substream->runtime->channels; in davinci_mcasp_delay()
1210 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_hw_params() local
1243 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); in davinci_mcasp_hw_params()
1244 return -EINVAL; in davinci_mcasp_hw_params()
1247 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); in davinci_mcasp_hw_params()
1252 * If mcasp is BCLK master, and a BCLK divider was not provided by in davinci_mcasp_hw_params()
1255 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_hw_params()
1256 int slots = mcasp->tdm_slots; in davinci_mcasp_hw_params()
1261 if (mcasp->slot_width) in davinci_mcasp_hw_params()
1262 sbits = mcasp->slot_width; in davinci_mcasp_hw_params()
1264 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) in davinci_mcasp_hw_params()
1269 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, in davinci_mcasp_hw_params()
1273 ret = mcasp_common_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1278 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_hw_params()
1279 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); in davinci_mcasp_hw_params()
1281 ret = mcasp_i2s_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1287 davinci_config_channel_size(mcasp, word_length); in davinci_mcasp_hw_params()
1289 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_hw_params()
1290 mcasp->channels = channels; in davinci_mcasp_hw_params()
1291 if (!mcasp->max_format_width) in davinci_mcasp_hw_params()
1292 mcasp->max_format_width = word_length; in davinci_mcasp_hw_params()
1301 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_trigger() local
1308 davinci_mcasp_start(mcasp, substream->stream); in davinci_mcasp_trigger()
1313 davinci_mcasp_stop(mcasp, substream->stream); in davinci_mcasp_trigger()
1317 ret = -EINVAL; in davinci_mcasp_trigger()
1326 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_slot_width()
1333 slot_width = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_slot_width()
1349 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_format_width()
1356 format_width = rd->mcasp->max_format_width; in davinci_mcasp_hw_rule_format_width()
1379 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_rate()
1383 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_rate()
1387 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_rate()
1388 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_rate()
1400 if (rd->mcasp->auxclk_fs_ratio) in davinci_mcasp_hw_rule_rate()
1402 rd->mcasp->auxclk_fs_ratio; in davinci_mcasp_hw_rule_rate()
1404 sysclk_freq = rd->mcasp->sysclk_freq; in davinci_mcasp_hw_rule_rate()
1406 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, in davinci_mcasp_hw_rule_rate()
1418 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_rate()
1419 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", in davinci_mcasp_hw_rule_rate()
1420 ri->min, ri->max, range.min, range.max, sbits, slots); in davinci_mcasp_hw_rule_rate()
1422 return snd_interval_refine(hw_param_interval(params, rule->var), in davinci_mcasp_hw_rule_rate()
1429 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_format()
1433 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_format()
1445 if (rd->mcasp->auxclk_fs_ratio) in davinci_mcasp_hw_rule_format()
1447 rd->mcasp->auxclk_fs_ratio; in davinci_mcasp_hw_rule_format()
1449 sysclk_freq = rd->mcasp->sysclk_freq; in davinci_mcasp_hw_rule_format()
1451 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_format()
1452 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_format()
1454 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, in davinci_mcasp_hw_rule_format()
1463 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_format()
1475 u8 numevt = *((u8 *)rule->private); in davinci_mcasp_hw_rule_min_periodsize()
1488 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_startup() local
1490 &mcasp->ruledata[substream->stream]; in davinci_mcasp_startup()
1493 int tdm_slots = mcasp->tdm_slots; in davinci_mcasp_startup()
1497 if (mcasp->substreams[substream->stream]) in davinci_mcasp_startup()
1498 return -EBUSY; in davinci_mcasp_startup()
1500 mcasp->substreams[substream->stream] = substream; in davinci_mcasp_startup()
1502 if (mcasp->tdm_mask[substream->stream]) in davinci_mcasp_startup()
1503 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); in davinci_mcasp_startup()
1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_startup()
1512 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in davinci_mcasp_startup()
1517 for (i = 0; i < mcasp->num_serializer; i++) { in davinci_mcasp_startup()
1518 if (mcasp->serial_dir[i] == dir) in davinci_mcasp_startup()
1521 ruledata->serializers = max_channels; in davinci_mcasp_startup()
1522 ruledata->mcasp = mcasp; in davinci_mcasp_startup()
1531 if (mcasp->channels && mcasp->channels < max_channels && in davinci_mcasp_startup()
1532 ruledata->serializers == 1) in davinci_mcasp_startup()
1533 max_channels = mcasp->channels; in davinci_mcasp_startup()
1541 snd_pcm_hw_constraint_minmax(substream->runtime, in davinci_mcasp_startup()
1545 snd_pcm_hw_constraint_list(substream->runtime, in davinci_mcasp_startup()
1547 &mcasp->chconstr[substream->stream]); in davinci_mcasp_startup()
1549 if (mcasp->max_format_width) { in davinci_mcasp_startup()
1554 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1558 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1562 else if (mcasp->slot_width) { in davinci_mcasp_startup()
1564 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1568 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1577 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_startup()
1578 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1582 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1585 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1589 SNDRV_PCM_HW_PARAM_RATE, -1); in davinci_mcasp_startup()
1594 numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? in davinci_mcasp_startup()
1595 &mcasp->txnumevt : in davinci_mcasp_startup()
1596 &mcasp->rxnumevt; in davinci_mcasp_startup()
1597 snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1600 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); in davinci_mcasp_startup()
1608 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_shutdown() local
1610 mcasp->substreams[substream->stream] = NULL; in davinci_mcasp_shutdown()
1611 mcasp->active_serializers[substream->stream] = 0; in davinci_mcasp_shutdown()
1613 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_shutdown()
1617 mcasp->channels = 0; in davinci_mcasp_shutdown()
1618 mcasp->max_format_width = 0; in davinci_mcasp_shutdown()
1625 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in davinci_mcasp_iec958_info()
1626 uinfo->count = 1; in davinci_mcasp_iec958_info()
1635 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_iec958_get() local
1637 memcpy(uctl->value.iec958.status, &mcasp->iec958_status, in davinci_mcasp_iec958_get()
1638 sizeof(mcasp->iec958_status)); in davinci_mcasp_iec958_get()
1647 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_iec958_put() local
1649 memcpy(&mcasp->iec958_status, uctl->value.iec958.status, in davinci_mcasp_iec958_put()
1650 sizeof(mcasp->iec958_status)); in davinci_mcasp_iec958_put()
1659 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_iec958_con_mask_get() local
1661 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status)); in davinci_mcasp_iec958_con_mask_get()
1683 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp) in davinci_mcasp_init_iec958_status() argument
1685 unsigned char *cs = (u8 *)&mcasp->iec958_status; in davinci_mcasp_init_iec958_status()
1695 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_dai_probe() local
1699 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]); in davinci_mcasp_dai_probe()
1701 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_dai_probe()
1702 davinci_mcasp_init_iec958_status(mcasp); in davinci_mcasp_dai_probe()
1738 .name = "davinci-mcasp.0",
1758 .name = "davinci-mcasp.1",
1773 .name = "davinci-mcasp",
1811 .compatible = "ti,dm646x-mcasp-audio",
1815 .compatible = "ti,da830-mcasp-audio",
1819 .compatible = "ti,am33xx-mcasp-audio",
1823 .compatible = "ti,dra7-mcasp-audio",
1827 .compatible = "ti,omap4-mcasp-audio",
1836 struct device_node *node = pdev->dev.of_node; in mcasp_reparent_fck()
1848 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); in mcasp_reparent_fck()
1850 gfclk = clk_get(&pdev->dev, "fck"); in mcasp_reparent_fck()
1852 dev_err(&pdev->dev, "failed to get fck\n"); in mcasp_reparent_fck()
1858 dev_err(&pdev->dev, "failed to get parent clock\n"); in mcasp_reparent_fck()
1865 dev_err(&pdev->dev, "failed to reparent fck\n"); in mcasp_reparent_fck()
1876 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) in davinci_mcasp_have_gpiochip() argument
1879 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller"); in davinci_mcasp_have_gpiochip()
1885 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, in davinci_mcasp_get_config() argument
1888 struct device_node *np = pdev->dev.of_node; in davinci_mcasp_get_config()
1891 device_get_match_data(&pdev->dev); in davinci_mcasp_get_config()
1896 if (pdev->dev.platform_data) { in davinci_mcasp_get_config()
1897 pdata = pdev->dev.platform_data; in davinci_mcasp_get_config()
1898 pdata->dismod = DISMOD_LOW; in davinci_mcasp_get_config()
1901 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata), in davinci_mcasp_get_config()
1904 return -ENOMEM; in davinci_mcasp_get_config()
1906 dev_err(&pdev->dev, "No compatible match found\n"); in davinci_mcasp_get_config()
1907 return -EINVAL; in davinci_mcasp_get_config()
1910 if (of_property_read_u32(np, "op-mode", &val) == 0) { in davinci_mcasp_get_config()
1911 pdata->op_mode = val; in davinci_mcasp_get_config()
1913 mcasp->missing_audio_param = true; in davinci_mcasp_get_config()
1917 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { in davinci_mcasp_get_config()
1919 dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n"); in davinci_mcasp_get_config()
1920 return -EINVAL; in davinci_mcasp_get_config()
1923 pdata->tdm_slots = val; in davinci_mcasp_get_config()
1924 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_get_config()
1925 mcasp->missing_audio_param = true; in davinci_mcasp_get_config()
1929 of_serial_dir32 = of_get_property(np, "serial-dir", &val); in davinci_mcasp_get_config()
1932 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, in davinci_mcasp_get_config()
1936 return -ENOMEM; in davinci_mcasp_get_config()
1941 pdata->num_serializer = val; in davinci_mcasp_get_config()
1942 pdata->serial_dir = of_serial_dir; in davinci_mcasp_get_config()
1944 mcasp->missing_audio_param = true; in davinci_mcasp_get_config()
1948 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) in davinci_mcasp_get_config()
1949 pdata->txnumevt = val; in davinci_mcasp_get_config()
1951 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) in davinci_mcasp_get_config()
1952 pdata->rxnumevt = val; in davinci_mcasp_get_config()
1954 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) in davinci_mcasp_get_config()
1955 mcasp->auxclk_fs_ratio = val; in davinci_mcasp_get_config()
1959 pdata->dismod = DISMOD_VAL(val); in davinci_mcasp_get_config()
1961 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); in davinci_mcasp_get_config()
1962 pdata->dismod = DISMOD_LOW; in davinci_mcasp_get_config()
1965 pdata->dismod = DISMOD_LOW; in davinci_mcasp_get_config()
1969 mcasp->pdata = pdata; in davinci_mcasp_get_config()
1971 if (mcasp->missing_audio_param) { in davinci_mcasp_get_config()
1972 if (davinci_mcasp_have_gpiochip(mcasp)) { in davinci_mcasp_get_config()
1973 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); in davinci_mcasp_get_config()
1977 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); in davinci_mcasp_get_config()
1978 return -ENODEV; in davinci_mcasp_get_config()
1981 mcasp->op_mode = pdata->op_mode; in davinci_mcasp_get_config()
1983 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_get_config()
1984 if (pdata->tdm_slots < 2) { in davinci_mcasp_get_config()
1985 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", in davinci_mcasp_get_config()
1986 pdata->tdm_slots); in davinci_mcasp_get_config()
1987 mcasp->tdm_slots = 2; in davinci_mcasp_get_config()
1988 } else if (pdata->tdm_slots > 32) { in davinci_mcasp_get_config()
1989 dev_warn(&pdev->dev, "invalid tdm slots: %d\n", in davinci_mcasp_get_config()
1990 pdata->tdm_slots); in davinci_mcasp_get_config()
1991 mcasp->tdm_slots = 32; in davinci_mcasp_get_config()
1993 mcasp->tdm_slots = pdata->tdm_slots; in davinci_mcasp_get_config()
1996 mcasp->tdm_slots = 32; in davinci_mcasp_get_config()
1999 mcasp->num_serializer = pdata->num_serializer; in davinci_mcasp_get_config()
2001 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, in davinci_mcasp_get_config()
2002 mcasp->num_serializer, sizeof(u32), in davinci_mcasp_get_config()
2004 if (!mcasp->context.xrsr_regs) in davinci_mcasp_get_config()
2005 return -ENOMEM; in davinci_mcasp_get_config()
2007 mcasp->serial_dir = pdata->serial_dir; in davinci_mcasp_get_config()
2008 mcasp->version = pdata->version; in davinci_mcasp_get_config()
2009 mcasp->txnumevt = pdata->txnumevt; in davinci_mcasp_get_config()
2010 mcasp->rxnumevt = pdata->rxnumevt; in davinci_mcasp_get_config()
2011 mcasp->dismod = pdata->dismod; in davinci_mcasp_get_config()
2023 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) in davinci_mcasp_get_dma_type() argument
2029 if (!mcasp->dev->of_node) in davinci_mcasp_get_dma_type()
2032 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; in davinci_mcasp_get_dma_type()
2033 chan = dma_request_chan(mcasp->dev, tmp); in davinci_mcasp_get_dma_type()
2035 return dev_err_probe(mcasp->dev, PTR_ERR(chan), in davinci_mcasp_get_dma_type()
2037 if (WARN_ON(!chan->device || !chan->device->dev)) { in davinci_mcasp_get_dma_type()
2039 return -EINVAL; in davinci_mcasp_get_dma_type()
2042 if (chan->device->dev->of_node) in davinci_mcasp_get_dma_type()
2043 ret = of_property_read_string(chan->device->dev->of_node, in davinci_mcasp_get_dma_type()
2046 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); in davinci_mcasp_get_dma_type()
2052 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); in davinci_mcasp_get_dma_type()
2068 if (pdata->version != MCASP_VERSION_4) in davinci_mcasp_txdma_offset()
2069 return pdata->tx_dma_offset; in davinci_mcasp_txdma_offset()
2071 for (i = 0; i < pdata->num_serializer; i++) { in davinci_mcasp_txdma_offset()
2072 if (pdata->serial_dir[i] == TX_MODE) { in davinci_mcasp_txdma_offset()
2091 if (pdata->version != MCASP_VERSION_4) in davinci_mcasp_rxdma_offset()
2092 return pdata->rx_dma_offset; in davinci_mcasp_rxdma_offset()
2094 for (i = 0; i < pdata->num_serializer; i++) { in davinci_mcasp_rxdma_offset()
2095 if (pdata->serial_dir[i] == RX_MODE) { in davinci_mcasp_rxdma_offset()
2112 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_request() local
2114 if (mcasp->num_serializer && offset < mcasp->num_serializer && in davinci_mcasp_gpio_request()
2115 mcasp->serial_dir[offset] != INACTIVE_MODE) { in davinci_mcasp_gpio_request()
2116 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); in davinci_mcasp_gpio_request()
2117 return -EBUSY; in davinci_mcasp_gpio_request()
2121 return pm_runtime_resume_and_get(mcasp->dev); in davinci_mcasp_gpio_request()
2126 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_free() local
2129 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_free()
2131 /* Set the pin as McASP pin */ in davinci_mcasp_gpio_free()
2132 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_free()
2134 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_gpio_free()
2140 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_direction_out() local
2144 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2146 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2148 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); in davinci_mcasp_gpio_direction_out()
2151 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2154 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2163 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_set() local
2166 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_set()
2168 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_set()
2174 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_direction_in() local
2177 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); in davinci_mcasp_gpio_direction_in()
2180 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_direction_in()
2183 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_direction_in()
2191 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_get() local
2194 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); in davinci_mcasp_gpio_get()
2204 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_get_direction() local
2207 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); in davinci_mcasp_gpio_get_direction()
2223 .base = -1,
2227 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) in davinci_mcasp_init_gpiochip() argument
2229 if (!davinci_mcasp_have_gpiochip(mcasp)) in davinci_mcasp_init_gpiochip()
2232 mcasp->gpio_chip = davinci_mcasp_template_chip; in davinci_mcasp_init_gpiochip()
2233 mcasp->gpio_chip.label = dev_name(mcasp->dev); in davinci_mcasp_init_gpiochip()
2234 mcasp->gpio_chip.parent = mcasp->dev; in davinci_mcasp_init_gpiochip()
2236 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); in davinci_mcasp_init_gpiochip()
2240 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) in davinci_mcasp_init_gpiochip() argument
2250 struct davinci_mcasp *mcasp; in davinci_mcasp_probe() local
2255 if (!pdev->dev.platform_data && !pdev->dev.of_node) { in davinci_mcasp_probe()
2256 dev_err(&pdev->dev, "No platform data supplied\n"); in davinci_mcasp_probe()
2257 return -EINVAL; in davinci_mcasp_probe()
2260 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), in davinci_mcasp_probe()
2262 if (!mcasp) in davinci_mcasp_probe()
2263 return -ENOMEM; in davinci_mcasp_probe()
2267 dev_warn(&pdev->dev, in davinci_mcasp_probe()
2271 dev_err(&pdev->dev, "no mem resource?\n"); in davinci_mcasp_probe()
2272 return -ENODEV; in davinci_mcasp_probe()
2276 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); in davinci_mcasp_probe()
2277 if (IS_ERR(mcasp->base)) in davinci_mcasp_probe()
2278 return PTR_ERR(mcasp->base); in davinci_mcasp_probe()
2280 dev_set_drvdata(&pdev->dev, mcasp); in davinci_mcasp_probe()
2281 pm_runtime_enable(&pdev->dev); in davinci_mcasp_probe()
2283 mcasp->dev = &pdev->dev; in davinci_mcasp_probe()
2284 ret = davinci_mcasp_get_config(mcasp, pdev); in davinci_mcasp_probe()
2288 /* All PINS as McASP */ in davinci_mcasp_probe()
2289 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_probe()
2290 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); in davinci_mcasp_probe()
2291 pm_runtime_put(mcasp->dev); in davinci_mcasp_probe()
2293 /* Skip audio related setup code if the configuration is not adequat */ in davinci_mcasp_probe()
2294 if (mcasp->missing_audio_param) in davinci_mcasp_probe()
2299 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", in davinci_mcasp_probe()
2300 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2302 ret = -ENOMEM; in davinci_mcasp_probe()
2305 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2308 irq_name, mcasp); in davinci_mcasp_probe()
2310 dev_err(&pdev->dev, "common IRQ request failed\n"); in davinci_mcasp_probe()
2314 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
2315 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
2320 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", in davinci_mcasp_probe()
2321 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2323 ret = -ENOMEM; in davinci_mcasp_probe()
2326 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2328 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
2330 dev_err(&pdev->dev, "RX IRQ request failed\n"); in davinci_mcasp_probe()
2334 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
2339 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", in davinci_mcasp_probe()
2340 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2342 ret = -ENOMEM; in davinci_mcasp_probe()
2345 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2347 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
2349 dev_err(&pdev->dev, "TX IRQ request failed\n"); in davinci_mcasp_probe()
2353 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
2358 mcasp->dat_port = true; in davinci_mcasp_probe()
2360 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
2361 dma_data->filter_data = "tx"; in davinci_mcasp_probe()
2363 dma_data->addr = dat->start; in davinci_mcasp_probe()
2368 if (mcasp->version == MCASP_VERSION_OMAP) in davinci_mcasp_probe()
2369 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata); in davinci_mcasp_probe()
2371 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); in davinci_mcasp_probe()
2376 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_probe()
2377 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
2378 dma_data->filter_data = "rx"; in davinci_mcasp_probe()
2380 dma_data->addr = dat->start; in davinci_mcasp_probe()
2382 dma_data->addr = in davinci_mcasp_probe()
2383 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); in davinci_mcasp_probe()
2386 if (mcasp->version < MCASP_VERSION_3) { in davinci_mcasp_probe()
2387 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; in davinci_mcasp_probe()
2388 /* dma_params->dma_addr is pointing to the data port address */ in davinci_mcasp_probe()
2389 mcasp->dat_port = true; in davinci_mcasp_probe()
2391 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; in davinci_mcasp_probe()
2401 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = in davinci_mcasp_probe()
2402 devm_kcalloc(mcasp->dev, in davinci_mcasp_probe()
2403 32 + mcasp->num_serializer - 1, in davinci_mcasp_probe()
2407 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = in davinci_mcasp_probe()
2408 devm_kcalloc(mcasp->dev, in davinci_mcasp_probe()
2409 32 + mcasp->num_serializer - 1, in davinci_mcasp_probe()
2413 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || in davinci_mcasp_probe()
2414 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { in davinci_mcasp_probe()
2415 ret = -ENOMEM; in davinci_mcasp_probe()
2419 ret = davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_probe()
2425 ret = davinci_mcasp_get_dma_type(mcasp); in davinci_mcasp_probe()
2428 ret = edma_pcm_platform_register(&pdev->dev); in davinci_mcasp_probe()
2431 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) in davinci_mcasp_probe()
2432 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); in davinci_mcasp_probe()
2434 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL); in davinci_mcasp_probe()
2437 ret = udma_pcm_platform_register(&pdev->dev); in davinci_mcasp_probe()
2440 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); in davinci_mcasp_probe()
2442 case -EPROBE_DEFER: in davinci_mcasp_probe()
2447 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); in davinci_mcasp_probe()
2451 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, in davinci_mcasp_probe()
2452 &davinci_mcasp_dai[mcasp->op_mode], 1); in davinci_mcasp_probe()
2458 ret = davinci_mcasp_init_gpiochip(mcasp); in davinci_mcasp_probe()
2460 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); in davinci_mcasp_probe()
2466 pm_runtime_disable(&pdev->dev); in davinci_mcasp_probe()
2472 pm_runtime_disable(&pdev->dev); in davinci_mcasp_remove()
2478 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); in davinci_mcasp_runtime_suspend() local
2479 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_runtime_suspend()
2484 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); in davinci_mcasp_runtime_suspend()
2486 if (mcasp->txnumevt) { in davinci_mcasp_runtime_suspend()
2487 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_runtime_suspend()
2488 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_runtime_suspend()
2490 if (mcasp->rxnumevt) { in davinci_mcasp_runtime_suspend()
2491 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_runtime_suspend()
2492 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_runtime_suspend()
2495 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_runtime_suspend()
2496 context->xrsr_regs[i] = mcasp_get_reg(mcasp, in davinci_mcasp_runtime_suspend()
2504 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); in davinci_mcasp_runtime_resume() local
2505 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_runtime_resume()
2510 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); in davinci_mcasp_runtime_resume()
2512 if (mcasp->txnumevt) { in davinci_mcasp_runtime_resume()
2513 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_runtime_resume()
2514 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); in davinci_mcasp_runtime_resume()
2516 if (mcasp->rxnumevt) { in davinci_mcasp_runtime_resume()
2517 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_runtime_resume()
2518 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); in davinci_mcasp_runtime_resume()
2521 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_runtime_resume()
2522 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in davinci_mcasp_runtime_resume()
2523 context->xrsr_regs[i]); in davinci_mcasp_runtime_resume()
2540 .name = "davinci-mcasp",
2549 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");