Lines Matching +full:non +full:- +full:zero
1 // SPDX-License-Identifier: GPL-2.0
15 __description("SDIV32, non-zero imm divisor, check 1")
16 __success __success_unpriv __retval(-20)
20 w0 = -41; \ in sdiv32_non_zero_imm_1()
27 __description("SDIV32, non-zero imm divisor, check 2")
28 __success __success_unpriv __retval(-20)
33 w0 s/= -2; \ in sdiv32_non_zero_imm_2()
39 __description("SDIV32, non-zero imm divisor, check 3")
44 w0 = -41; \ in sdiv32_non_zero_imm_3()
45 w0 s/= -2; \ in sdiv32_non_zero_imm_3()
51 __description("SDIV32, non-zero imm divisor, check 4")
52 __success __success_unpriv __retval(-21)
56 w0 = -42; \ in sdiv32_non_zero_imm_4()
63 __description("SDIV32, non-zero imm divisor, check 5")
64 __success __success_unpriv __retval(-21)
69 w0 s/= -2; \ in sdiv32_non_zero_imm_5()
75 __description("SDIV32, non-zero imm divisor, check 6")
80 w0 = -42; \ in sdiv32_non_zero_imm_6()
81 w0 s/= -2; \ in sdiv32_non_zero_imm_6()
87 __description("SDIV32, non-zero imm divisor, check 7")
99 __description("SDIV32, non-zero imm divisor, check 8")
111 __description("SDIV32, non-zero reg divisor, check 1")
112 __success __success_unpriv __retval(-20)
116 w0 = -41; \ in sdiv32_non_zero_reg_1()
124 __description("SDIV32, non-zero reg divisor, check 2")
125 __success __success_unpriv __retval(-20)
130 w1 = -2; \ in sdiv32_non_zero_reg_2()
137 __description("SDIV32, non-zero reg divisor, check 3")
142 w0 = -41; \ in sdiv32_non_zero_reg_3()
143 w1 = -2; \ in sdiv32_non_zero_reg_3()
150 __description("SDIV32, non-zero reg divisor, check 4")
151 __success __success_unpriv __retval(-21)
155 w0 = -42; \ in sdiv32_non_zero_reg_4()
163 __description("SDIV32, non-zero reg divisor, check 5")
164 __success __success_unpriv __retval(-21)
169 w1 = -2; \ in sdiv32_non_zero_reg_5()
176 __description("SDIV32, non-zero reg divisor, check 6")
181 w0 = -42; \ in sdiv32_non_zero_reg_6()
182 w1 = -2; \ in sdiv32_non_zero_reg_6()
189 __description("SDIV32, non-zero reg divisor, check 7")
202 __description("SDIV32, non-zero reg divisor, check 8")
215 __description("SDIV64, non-zero imm divisor, check 1")
216 __success __success_unpriv __retval(-20)
220 r0 = -41; \ in sdiv64_non_zero_imm_1()
227 __description("SDIV64, non-zero imm divisor, check 2")
228 __success __success_unpriv __retval(-20)
233 r0 s/= -2; \ in sdiv64_non_zero_imm_2()
239 __description("SDIV64, non-zero imm divisor, check 3")
244 r0 = -41; \ in sdiv64_non_zero_imm_3()
245 r0 s/= -2; \ in sdiv64_non_zero_imm_3()
251 __description("SDIV64, non-zero imm divisor, check 4")
252 __success __success_unpriv __retval(-21)
256 r0 = -42; \ in sdiv64_non_zero_imm_4()
263 __description("SDIV64, non-zero imm divisor, check 5")
264 __success __success_unpriv __retval(-21)
269 r0 s/= -2; \ in sdiv64_non_zero_imm_5()
275 __description("SDIV64, non-zero imm divisor, check 6")
280 r0 = -42; \ in sdiv64_non_zero_imm_6()
281 r0 s/= -2; \ in sdiv64_non_zero_imm_6()
287 __description("SDIV64, non-zero reg divisor, check 1")
288 __success __success_unpriv __retval(-20)
292 r0 = -41; \ in sdiv64_non_zero_reg_1()
300 __description("SDIV64, non-zero reg divisor, check 2")
301 __success __success_unpriv __retval(-20)
306 r1 = -2; \ in sdiv64_non_zero_reg_2()
313 __description("SDIV64, non-zero reg divisor, check 3")
318 r0 = -41; \ in sdiv64_non_zero_reg_3()
319 r1 = -2; \ in sdiv64_non_zero_reg_3()
326 __description("SDIV64, non-zero reg divisor, check 4")
327 __success __success_unpriv __retval(-21)
331 r0 = -42; \ in sdiv64_non_zero_reg_4()
339 __description("SDIV64, non-zero reg divisor, check 5")
340 __success __success_unpriv __retval(-21)
345 r1 = -2; \ in sdiv64_non_zero_reg_5()
352 __description("SDIV64, non-zero reg divisor, check 6")
357 r0 = -42; \ in sdiv64_non_zero_reg_6()
358 r1 = -2; \ in sdiv64_non_zero_reg_6()
365 __description("SMOD32, non-zero imm divisor, check 1")
366 __success __success_unpriv __retval(-1)
370 w0 = -41; \ in smod32_non_zero_imm_1()
377 __description("SMOD32, non-zero imm divisor, check 2")
383 w0 s%%= -2; \ in smod32_non_zero_imm_2()
389 __description("SMOD32, non-zero imm divisor, check 3")
390 __success __success_unpriv __retval(-1)
394 w0 = -41; \ in smod32_non_zero_imm_3()
395 w0 s%%= -2; \ in smod32_non_zero_imm_3()
401 __description("SMOD32, non-zero imm divisor, check 4")
406 w0 = -42; \ in smod32_non_zero_imm_4()
413 __description("SMOD32, non-zero imm divisor, check 5")
419 w0 s%%= -2; \ in smod32_non_zero_imm_5()
425 __description("SMOD32, non-zero imm divisor, check 6")
430 w0 = -42; \ in smod32_non_zero_imm_6()
431 w0 s%%= -2; \ in smod32_non_zero_imm_6()
437 __description("SMOD32, non-zero reg divisor, check 1")
438 __success __success_unpriv __retval(-1)
442 w0 = -41; \ in smod32_non_zero_reg_1()
450 __description("SMOD32, non-zero reg divisor, check 2")
456 w1 = -2; \ in smod32_non_zero_reg_2()
463 __description("SMOD32, non-zero reg divisor, check 3")
464 __success __success_unpriv __retval(-1)
468 w0 = -41; \ in smod32_non_zero_reg_3()
469 w1 = -2; \ in smod32_non_zero_reg_3()
476 __description("SMOD32, non-zero reg divisor, check 4")
481 w0 = -42; \ in smod32_non_zero_reg_4()
489 __description("SMOD32, non-zero reg divisor, check 5")
495 w1 = -2; \ in smod32_non_zero_reg_5()
502 __description("SMOD32, non-zero reg divisor, check 6")
507 w0 = -42; \ in smod32_non_zero_reg_6()
508 w1 = -2; \ in smod32_non_zero_reg_6()
515 __description("SMOD64, non-zero imm divisor, check 1")
516 __success __success_unpriv __retval(-1)
520 r0 = -41; \ in smod64_non_zero_imm_1()
527 __description("SMOD64, non-zero imm divisor, check 2")
533 r0 s%%= -2; \ in smod64_non_zero_imm_2()
539 __description("SMOD64, non-zero imm divisor, check 3")
540 __success __success_unpriv __retval(-1)
544 r0 = -41; \ in smod64_non_zero_imm_3()
545 r0 s%%= -2; \ in smod64_non_zero_imm_3()
551 __description("SMOD64, non-zero imm divisor, check 4")
556 r0 = -42; \ in smod64_non_zero_imm_4()
563 __description("SMOD64, non-zero imm divisor, check 5")
564 __success __success_unpriv __retval(-0)
569 r0 s%%= -2; \ in smod64_non_zero_imm_5()
575 __description("SMOD64, non-zero imm divisor, check 6")
580 r0 = -42; \ in smod64_non_zero_imm_6()
581 r0 s%%= -2; \ in smod64_non_zero_imm_6()
587 __description("SMOD64, non-zero imm divisor, check 7")
599 __description("SMOD64, non-zero imm divisor, check 8")
611 __description("SMOD64, non-zero reg divisor, check 1")
612 __success __success_unpriv __retval(-1)
616 r0 = -41; \ in smod64_non_zero_reg_1()
624 __description("SMOD64, non-zero reg divisor, check 2")
630 r1 = -2; \ in smod64_non_zero_reg_2()
637 __description("SMOD64, non-zero reg divisor, check 3")
638 __success __success_unpriv __retval(-1)
642 r0 = -41; \ in smod64_non_zero_reg_3()
643 r1 = -2; \ in smod64_non_zero_reg_3()
650 __description("SMOD64, non-zero reg divisor, check 4")
655 r0 = -42; \ in smod64_non_zero_reg_4()
663 __description("SMOD64, non-zero reg divisor, check 5")
669 r1 = -2; \ in smod64_non_zero_reg_5()
676 __description("SMOD64, non-zero reg divisor, check 6")
681 r0 = -42; \ in smod64_non_zero_reg_6()
682 r1 = -2; \ in smod64_non_zero_reg_6()
689 __description("SMOD64, non-zero reg divisor, check 7")
702 __description("SMOD64, non-zero reg divisor, check 8")
715 __description("SDIV32, zero divisor")
722 w2 = -1; \ in sdiv32_zero_divisor()
730 __description("SDIV64, zero divisor")
737 r2 = -1; \ in sdiv64_zero_divisor()
745 __description("SMOD32, zero divisor")
746 __success __success_unpriv __retval(-1)
752 w2 = -1; \ in smod32_zero_divisor()
760 __description("SMOD64, zero divisor")
761 __success __success_unpriv __retval(-1)
767 r2 = -1; \ in smod64_zero_divisor()
775 __description("SDIV64, overflow r/r, LLONG_MIN/-1")
779 __xlated("2: r3 = -1")
786 __xlated("9: r2 = -r2")
797 r3 = -1; \ in sdiv64_overflow_rr()
810 __description("SDIV64, r/r, small_val/-1")
811 __success __retval(-5)
814 __xlated("1: r3 = -1")
820 __xlated("7: r2 = -r2")
829 r3 = -1; \ in sdiv64_rr_divisor_neg_1()
839 __description("SDIV64, overflow r/i, LLONG_MIN/-1")
844 __xlated("3: r2 = -r2")
854 r2 s/= -1; \ in sdiv64_overflow_ri()
865 __description("SDIV64, r/i, small_val/-1")
866 __success __retval(-5)
870 __xlated("2: r2 = -r2")
878 r2 s/= -1; \ in sdiv64_ri_divisor_neg_1()
887 __description("SDIV32, overflow r/r, INT_MIN/-1")
890 __xlated("0: w2 = -2147483648")
891 __xlated("1: w3 = -1")
898 __xlated("8: w2 = -w2")
909 w3 = -1; \ in sdiv32_overflow_rr()
922 __description("SDIV32, r/r, small_val/-1")
925 __xlated("0: w2 = -5")
926 __xlated("1: w3 = -1")
933 __xlated("8: w2 = -w2")
941 w2 = -5; \ in sdiv32_rr_divisor_neg_1()
942 w3 = -1; \ in sdiv32_rr_divisor_neg_1()
953 __description("SDIV32, overflow r/i, INT_MIN/-1")
956 __xlated("0: w2 = -2147483648")
958 __xlated("2: w2 = -w2")
968 w2 s/= -1; \ in sdiv32_overflow_ri()
979 __description("SDIV32, r/i, small_val/-1")
980 __success __retval(-5)
984 __xlated("2: w2 = -w2")
992 w2 s/= -1; \ in sdiv32_ri_divisor_neg_1()
1001 __description("SMOD64, overflow r/r, LLONG_MIN/-1")
1005 __xlated("2: r3 = -1")
1020 r3 = -1; \ in smod64_overflow_rr()
1031 __description("SMOD64, r/r, small_val/-1")
1035 __xlated("1: r3 = -1")
1050 r3 = -1; \ in smod64_rr_divisor_neg_1()
1061 __description("SMOD64, overflow r/i, LLONG_MIN/-1")
1074 r2 s%%= -1; \ in smod64_overflow_ri()
1083 __description("SMOD64, r/i, small_val/-1")
1096 r2 s%%= -1; \ in smod64_ri_divisor_neg_1()
1105 __description("SMOD32, overflow r/r, INT_MIN/-1")
1108 __xlated("0: w2 = -2147483648")
1109 __xlated("1: w3 = -1")
1126 w3 = -1; \ in smod32_overflow_rr()
1137 __description("SMOD32, r/r, small_val/-1")
1140 __xlated("0: w2 = -5")
1141 __xlated("1: w3 = -1")
1157 w2 = -5; \ in smod32_rr_divisor_neg_1()
1158 w3 = -1; \ in smod32_rr_divisor_neg_1()
1169 __description("SMOD32, overflow r/i, INT_MIN/-1")
1172 __xlated("0: w2 = -2147483648")
1182 w2 s%%= -1; \ in smod32_overflow_ri()
1191 __description("SMOD32, r/i, small_val/-1")
1204 w2 s%%= -1; \ in smod32_ri_divisor_neg_1()