Lines Matching full:exception
20 * Bit '0' is set on Intel if the exception occurs while delivering a previous
21 * event/exception. AMD's wording is ambiguous, but presumably the bit is set
22 * if the exception occurs while delivering an external event, e.g. NMI or INTR,
141 * VMX disallows injecting an exception with error_code[31:16] != 0, in l1_vmx_code()
196 TEST_ASSERT(!events.exception.pending, in queue_ss_exception()
197 "Vector %d unexpectedlt pending", events.exception.nr); in queue_ss_exception()
198 TEST_ASSERT(!events.exception.injected, in queue_ss_exception()
199 "Vector %d unexpectedly injected", events.exception.nr); in queue_ss_exception()
202 events.exception.pending = !inject; in queue_ss_exception()
203 events.exception.injected = inject; in queue_ss_exception()
204 events.exception.nr = SS_VECTOR; in queue_ss_exception()
205 events.exception.has_error_code = true; in queue_ss_exception()
206 events.exception.error_code = SS_ERROR_CODE; in queue_ss_exception()
212 * when an exception is being queued for L2. Specifically, verify that KVM
213 * honors L1 exception intercept controls when a #SS is pending/injected,
250 TEST_ASSERT_EQ(events.exception.pending, true); in main()
251 TEST_ASSERT_EQ(events.exception.nr, SS_VECTOR); in main()
252 TEST_ASSERT_EQ(events.exception.has_error_code, true); in main()
253 TEST_ASSERT_EQ(events.exception.error_code, SS_ERROR_CODE); in main()